[llvm] 4cf0ddd - [ARM][MVE] Enable VMOVN for tail predication

[Sam Parker via llvm-commits]

Author: Sam Parker
Date: 2020-03-06T08:59:22Z
New Revision: 4cf0dddcc6f5122a847e5e319435f558e02d38c9

URL: https://github.com/llvm/llvm-project/commit/4cf0dddcc6f5122a847e5e319435f558e02d38c9
DIFF: https://github.com/llvm/llvm-project/commit/4cf0dddcc6f5122a847e5e319435f558e02d38c9.diff

LOG: [ARM][MVE] Enable VMOVN for tail predication

These instructions also don't exchange lanes, so make them legal.

Differential Revision: https://reviews.llvm.org/D75669

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMInstrMVE.td
    llvm/unittests/Target/ARM/MachineInstrTest.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index 65939fd5d7d3..152454005f84 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -4421,6 +4421,7 @@ class MVE_VxMOVxN<string iname, string suffix, bit bit_28, bit bit_17,
   let Inst{8} = 0b0;
   let Inst{7} = !if(!eq(bit_17, 0), 1, 0);
   let Inst{0} = 0b1;
+  let validForTailPredication = 1;
 }
 
 multiclass MVE_VxMOVxN_halves<string iname, string suffix,

diff  --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
index ff57cfb3d397..33e03f853f90 100644
--- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp
+++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
@@ -256,6 +256,10 @@ TEST(MachineInstrValidTailPredication, IsCorrect) {
     case MVE_VMOVimmi32:	
     case MVE_VMOVimmi64:
     case MVE_VMOVimmi8:	
+    case MVE_VMOVNi16bh:
+    case MVE_VMOVNi16th:
+    case MVE_VMOVNi32bh:
+    case MVE_VMOVNi32th:
     case MVE_VMULLBp16:
     case MVE_VMULLBp8:
     case MVE_VMULLBs16:
@@ -321,6 +325,18 @@ TEST(MachineInstrValidTailPredication, IsCorrect) {
     case MVE_VQNEGs16:
     case MVE_VQNEGs32:
     case MVE_VQNEGs8:
+    case MVE_VQMOVNs16bh:
+    case MVE_VQMOVNs16th:
+    case MVE_VQMOVNs32bh:
+    case MVE_VQMOVNs32th:
+    case MVE_VQMOVNu16bh:
+    case MVE_VQMOVNu16th:
+    case MVE_VQMOVNu32bh:
+    case MVE_VQMOVNu32th:
+    case MVE_VQMOVUNs16bh:
+    case MVE_VQMOVUNs16th:
+    case MVE_VQMOVUNs32bh:
+    case MVE_VQMOVUNs32th:
     case MVE_VQRSHL_by_vecs16:
     case MVE_VQRSHL_by_vecs32:
     case MVE_VQRSHL_by_vecs8: