[compiler-rt] 99a8cc2 - [compiler-rt][builtins][RISCV] Port __clear_cache to RISC-V Linux

[Luís Marques via llvm-commits]

Author: Luís Marques
Date: 2020-03-05T16:44:47Z
New Revision: 99a8cc2b7d89ff73a20aa3e0317fee8b5cb5cecb

URL: https://github.com/llvm/llvm-project/commit/99a8cc2b7d89ff73a20aa3e0317fee8b5cb5cecb
DIFF: https://github.com/llvm/llvm-project/commit/99a8cc2b7d89ff73a20aa3e0317fee8b5cb5cecb.diff

LOG: [compiler-rt][builtins][RISCV] Port __clear_cache to RISC-V Linux

Implements `__clear_cache` for RISC-V Linux. We can't just use `fence.i` on
Linux, because the Linux thread might be scheduled on another hart, and the
`fence.i` instruction only flushes the icache of the current hart.

Added: 
    

Modified: 
    compiler-rt/lib/builtins/clear_cache.c

Removed: 
    


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diff  --git a/compiler-rt/lib/builtins/clear_cache.c b/compiler-rt/lib/builtins/clear_cache.c
index e83e21254e85..72e02e613de5 100644
--- a/compiler-rt/lib/builtins/clear_cache.c
+++ b/compiler-rt/lib/builtins/clear_cache.c
@@ -147,6 +147,16 @@ void __clear_cache(void *start, void *end) {
 
   for (uintptr_t dword = start_dword; dword < end_dword; dword += dword_size)
     __asm__ volatile("flush %0" : : "r"(dword));
+#elif defined(__riscv) && defined(__linux__)
+#define __NR_riscv_flush_icache (244 + 15)
+  register void *start_reg __asm("a0") = start;
+  const register void *end_reg __asm("a1") = end;
+  const register long flags __asm("a2") = 0;
+  const register long syscall_nr __asm("a7") = __NR_riscv_flush_icache;
+  __asm __volatile("ecall"
+                   : "=r"(start_reg)
+                   : "r"(start_reg), "r"(end_reg), "r"(flags), "r"(syscall_nr));
+  assert(start_reg == 0 && "Cache flush syscall failed.");
 #else
 #if __APPLE__
   // On Darwin, sys_icache_invalidate() provides this functionality