[PATCH] D75553: [ARM] Constant long shift combines

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:14102
+      unsigned NewOpcode =
+          N->getOpcode() == ARMISD::LSLL ? ARMISD::LSRL : ARMISD::LSLL;
+      SDValue NewShift = DAG.getNode(NewOpcode, DL, N->getVTList(), Op0, Op1,
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samparker wrote:
> And why don't we have to worry about arithmetic shifts?
I think my argument was that any "shift right" becomes a "logical shift left", as the signedness doesn't end up mattering.


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  https://reviews.llvm.org/D75553/new/

https://reviews.llvm.org/D75553