[PATCH] D75504: [AMDGPU] moving vcc branch optimization into peephole

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas marked 2 inline comments as done.
cdevadas added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp:1017
   addPass(&SIRemoveShortExecBranchesID);
+  addPass(&PeepholeOptimizerID);
   addPass(&SIInsertSkipsPassID);
----------------
arsenm wrote:
> Should not need an extra run of this
The peephole is invoked earlier during SSAOptimization. It is required here to optimize the pattern introduced later. The lit test multilevel-break.ll has a similar opportunity in function multi_if_break_loop. 


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:2182
+
+    unsigned SReg = AMDGPU::NoRegister;
+    if (Op2.isReg()) {
----------------
arsenm wrote:
> Register, and initialization isn't needed
Are you saying the initialization is not required? 
SReg is not defined in all control-flows later.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75504/new/

https://reviews.llvm.org/D75504