[PATCH] D75203: [X86] Relax existing instructions to reduce the number of nops needed for alignment purposes

[Kan Shengchen via Phabricator via llvm-commits]

skan added inline comments.


================
Comment at: llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp:661
+  auto &STI = *RF.getSubtargetInfo();
+  bool is16BitMode = STI.getFeatureBits()[X86::Mode16Bit];
+  return getRelaxedOpcode(Inst, is16BitMode) != Inst.getOpcode();
----------------
Is16BitMode


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Comment at: llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp:802
+        // MCBoundaryAlignFragment(if exists) also marks the end of the branch.
+        for (int i = 0, N = BF.isFused() ? 2 : 1;
+             i != N && !isa<MCBoundaryAlignFragment>(F);
----------------
Capitalize i here otherwise clang tidy would report a warning


================
Comment at: llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp:811
+  // The layout is done. Mark every fragment as valid.
+  for (unsigned int i = 0, n = Layout.getSectionOrder().size(); i != n; ++i) {
+    MCSection &Section = *Layout.getSectionOrder()[i];
----------------
Capitalize i and N here otherwise clang tidy would report a warning


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75203/new/

https://reviews.llvm.org/D75203