[PATCH] D67694: [Power9] Fix the missing pseudo instruction scheduling information for power9

[Kit Barton via Phabricator via llvm-commits]

kbarton added a comment.

I think this is a good change. My only question is with the test case. If we can get the necessary information out of MIR, then I think it's better to write an MIR test case instead of relying on the debug output from the machine scheduler.



================
Comment at: llvm/test/CodeGen/PowerPC/pseudo-inst-latency.ll:2
+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -relocation-model=pic -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+
----------------
Could this be done as an MIR test instead of relying on the debug output from the machine scheduler?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67694/new/

https://reviews.llvm.org/D67694