[llvm] 0fafb4b - [Hexagon] Use BUILD_PAIR to expand i128 instead of doing arithmetic

[Krzysztof Parzyszek via llvm-commits]

Author: Krzysztof Parzyszek
Date: 2020-03-02T09:52:07-06:00
New Revision: 0fafb4beccc73bac01f0bfb3a46d0797f8051d40

URL: https://github.com/llvm/llvm-project/commit/0fafb4beccc73bac01f0bfb3a46d0797f8051d40
DIFF: https://github.com/llvm/llvm-project/commit/0fafb4beccc73bac01f0bfb3a46d0797f8051d40.diff

LOG: [Hexagon] Use BUILD_PAIR to expand i128 instead of doing arithmetic

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 4a53cc489184..5ab000df2db0 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -1565,14 +1565,7 @@ HexagonTargetLowering::LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const {
     if (BitWidth == 64)
       return Combines[0];
 
-    // It must be i128. I128 is not a legal type, so this part will be
-    // executed during type legalization. We need to generate code that
-    // the default expansion can break up into smaller pieces.
-    SDValue C0 = DAG.getZExtOrTrunc(Combines[0], dl, ResTy);
-    SDValue C1 = DAG.getNode(ISD::SHL, dl, ResTy,
-        DAG.getZExtOrTrunc(Combines[1], dl, ResTy),
-        DAG.getConstant(64, dl, MVT::i32));
-    return DAG.getNode(ISD::OR, dl, ResTy, C0, C1);
+    return DAG.getNode(ISD::BUILD_PAIR, dl, ResTy, Combines);
   }
 
   return Op;