[PATCH] D75388: Add a pass to identify certain shuffle_vector and transform it into target specific intrinsics.

[Wei Zhao via Phabricator via llvm-commits]

wxz2020 created this revision.
wxz2020 added reviewers: bogner, dorit.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls.
Herald added a project: LLVM.

E.g. An interleaved load (Factor = 4):

  %wide.vec = load <8 x i16>, <8 x i16>* %ptr
  %strided.vec = shuffle <8 x i16> %wide.vec, <8 x i16> undef, <2 x i32><i32 0, i32 4>

%v1 = uitofp <2 x i16> %strided.vec to <2 x double>

It can be transformed into a tbl1 intrinsic in AArch64 backend to avoid the high cost extract/insert sequences.

The change is also summarized in calculating InterleavedMemoryOpCost in loop vectorizer for decision in 
loop vectorization.

This change will give SPEC2017 538.imagick_r 11.5% performance boost.

Tested using:
%llvm/build/bin/llvm-lit ../../test/*

And there is no regression on the test.

And we also tested this on SPEC2017 whole suite and they all pass and there is no performance regression.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D75388

Files:
  llvm/include/llvm/Analysis/TargetTransformInfo.h
  llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
  llvm/include/llvm/Analysis/VectorUtils.h
  llvm/include/llvm/CodeGen/BasicTTIImpl.h
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Analysis/TargetTransformInfo.cpp
  llvm/lib/Analysis/VectorUtils.cpp
  llvm/lib/CodeGen/InterleavedAccessPass.cpp
  llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

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