[llvm] e0568ef - [VectorCombine] add tests for possible extract->shuffle; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2020-02-25T08:41:59-05:00
New Revision: e0568ef2c5c2e949ccfd5b66cc749fab8fa38e03

URL: https://github.com/llvm/llvm-project/commit/e0568ef2c5c2e949ccfd5b66cc749fab8fa38e03
DIFF: https://github.com/llvm/llvm-project/commit/e0568ef2c5c2e949ccfd5b66cc749fab8fa38e03.diff

LOG: [VectorCombine] add tests for possible extract->shuffle; NFC

Added: 
    

Modified: 
    llvm/test/Transforms/VectorCombine/X86/extract-binop.ll
    llvm/test/Transforms/VectorCombine/X86/extract-cmp.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/VectorCombine/X86/extract-binop.ll b/llvm/test/Transforms/VectorCombine/X86/extract-binop.ll
index 13c25ee5874a..30d0475437bd 100644
--- a/llvm/test/Transforms/VectorCombine/X86/extract-binop.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/extract-binop.ll
@@ -249,3 +249,29 @@ define i8 @ext0_ext1_add(<16 x i8> %x, <16 x i8> %y) {
   %r = add i8 %e0, %e1
   ret i8 %r
 }
+
+define i8 @ext5_ext0_add(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: @ext5_ext0_add(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 5
+; CHECK-NEXT:    [[E1:%.*]] = extractelement <16 x i8> [[Y:%.*]], i32 0
+; CHECK-NEXT:    [[R:%.*]] = sub i8 [[E0]], [[E1]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %e0 = extractelement <16 x i8> %x, i32 5
+  %e1 = extractelement <16 x i8> %y, i32 0
+  %r = sub i8 %e0, %e1
+  ret i8 %r
+}
+
+define i8 @ext5_ext6_add(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: @ext5_ext6_add(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 5
+; CHECK-NEXT:    [[E1:%.*]] = extractelement <16 x i8> [[Y:%.*]], i32 6
+; CHECK-NEXT:    [[R:%.*]] = and i8 [[E0]], [[E1]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %e0 = extractelement <16 x i8> %x, i32 5
+  %e1 = extractelement <16 x i8> %y, i32 6
+  %r = and i8 %e0, %e1
+  ret i8 %r
+}

diff  --git a/llvm/test/Transforms/VectorCombine/X86/extract-cmp.ll b/llvm/test/Transforms/VectorCombine/X86/extract-cmp.ll
index 8d04af3c8105..bfbd79a72be4 100644
--- a/llvm/test/Transforms/VectorCombine/X86/extract-cmp.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/extract-cmp.ll
@@ -100,3 +100,42 @@ t:
 f:
   ret i32 0
 }
+
+define i1 @cmp01_v2f64(<2 x double> %x, <2 x double> %y) {
+; CHECK-LABEL: @cmp01_v2f64(
+; CHECK-NEXT:    [[X0:%.*]] = extractelement <2 x double> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[Y1:%.*]] = extractelement <2 x double> [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp oge double [[X0]], [[Y1]]
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %x0 = extractelement <2 x double> %x, i32 0
+  %y1 = extractelement <2 x double> %y, i32 1
+  %cmp = fcmp oge double %x0, %y1
+  ret i1 %cmp
+}
+
+define i1 @cmp10_v2f64(<2 x double> %x, <2 x double> %y) {
+; CHECK-LABEL: @cmp10_v2f64(
+; CHECK-NEXT:    [[X1:%.*]] = extractelement <2 x double> [[X:%.*]], i32 1
+; CHECK-NEXT:    [[Y0:%.*]] = extractelement <2 x double> [[Y:%.*]], i32 0
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp ule double [[X1]], [[Y0]]
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %x1 = extractelement <2 x double> %x, i32 1
+  %y0 = extractelement <2 x double> %y, i32 0
+  %cmp = fcmp ule double %x1, %y0
+  ret i1 %cmp
+}
+
+define i1 @cmp12_v4i32(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @cmp12_v4i32(
+; CHECK-NEXT:    [[X1:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 1
+; CHECK-NEXT:    [[Y2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i32 2
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X1]], [[Y2]]
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %x1 = extractelement <4 x i32> %x, i32 1
+  %y2 = extractelement <4 x i32> %y, i32 2
+  %cmp = icmp sgt i32 %x1, %y2
+  ret i1 %cmp
+}