[PATCH] D71701: [AArch64] Peephole optimization. Merge AND and TST instructions

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added a comment.

Nice one, that's very minimal now.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1682
+      const SDValue RHSOp = LHS.getOperand(1);
+      const SDValue LHSOp = LHS.getOperand(0);
+      const SDValue ANDSNode = DAG.getNode(AArch64ISD::ANDS, dl,
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Some real nits: there's probably very little benefit of declaring `RHSOp` and `LHSOp` here. For readability, it's probably better to just feed the `LHS.getOperand()` directly to `getNode()` 


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Comment at: llvm/test/CodeGen/AArch64/peephole-and-tst.ll:1
+; RUN: llc -mtriple=aarch64-linux-gnu %s -o %t; FileCheck %s --input-file=%t
+
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You don't need the temp file, probably this is enough:

  ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s


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Comment at: llvm/test/CodeGen/AArch64/peephole-and-tst.ll:2
+; RUN: llc -mtriple=aarch64-linux-gnu %s -o %t; FileCheck %s --input-file=%t
+
+%struct.anon = type { i32*, i32* }
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Probably good to add a test case where the AND has multiple users.


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Comment at: llvm/test/CodeGen/AArch64/peephole-and-tst.ll:16
+; CHECK-LABEL: test_func_i32:
+; CHECK-LABEL: .LBB0_2:
+; CHECK: ands [[DSTREG:w[0-9]+]], [[SRCREG1:w[0-9]+]], [[SRCREG2:w[0-9]+]]
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It's not wrong, but you don't need the second check-label here, that can be a normal check. And it's probably easier to just let script `utils/update_llc_test_checks.py` generate all the checks for you.


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  https://reviews.llvm.org/D71701/new/

https://reviews.llvm.org/D71701