[PATCH] D74306: [MIR][ARM] MachineOperand comments to print condition code names instead of constants

Sjoerd Meijer via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 24 06:23:07 PST 2020 

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7efabe5c7de4: [MIR][ARM] MachineOperand comments (authored by SjoerdMeijer).

Changed prior to commit:
  https://reviews.llvm.org/D74306?vs=245595&id=246195#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74306/new/

https://reviews.llvm.org/D74306

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/MIRParser/MILexer.cpp
  llvm/lib/CodeGen/MIRPrinter.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir
  llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
  llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
  llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
  llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
  llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
  llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
  llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
  llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
  llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir
  llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir
  llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir
  llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
  llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir
  llvm/test/CodeGen/ARM/GlobalISel/select-fp-const.mir
  llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir
  llvm/test/CodeGen/ARM/GlobalISel/select-neon.mir
  llvm/test/CodeGen/ARM/GlobalISel/select-pkhbt.mir
  llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
  llvm/test/CodeGen/ARM/GlobalISel/select-revsh.mir
  llvm/test/CodeGen/ARM/GlobalISel/thumb-instruction-select-cmp.mir
  llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir
  llvm/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir
  llvm/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir
  llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-pic.mir
  llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-ropi-rwpi.mir
  llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-static.mir
  llvm/test/CodeGen/ARM/GlobalISel/thumb-select-imm.mir
  llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
  llvm/test/CodeGen/ARM/GlobalISel/thumb-select-logical-ops.mir
  llvm/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir
  llvm/test/CodeGen/ARM/GlobalISel/thumb-select-shifts.mir
  llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir
  llvm/test/CodeGen/ARM/cmpxchg.mir
  llvm/test/CodeGen/ARM/codesize-ifcvt.mir
  llvm/test/CodeGen/ARM/constant-island-movwt.mir
  llvm/test/CodeGen/ARM/constant-islands-cfg.mir
  llvm/test/CodeGen/ARM/constant-islands-split-IT.mir
  llvm/test/CodeGen/ARM/expand-pseudos.mir
  llvm/test/CodeGen/ARM/fpoffset_overflow.mir
  llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
  llvm/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir
  llvm/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir
  llvm/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir
  llvm/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir
  llvm/test/CodeGen/ARM/ifcvt_triangleSameCvtNext.mir
  llvm/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir
  llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir
  llvm/test/CodeGen/ARM/load_store_opt_kill.mir
  llvm/test/CodeGen/ARM/load_store_opt_reg_limit.mir
  llvm/test/CodeGen/ARM/machine-copyprop.mir
  llvm/test/CodeGen/ARM/peephole-phi.mir
  llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir
  llvm/test/CodeGen/ARM/register-scavenger-exceptions.mir
  llvm/test/CodeGen/ARM/tail-dup-bundle.mir
  llvm/test/CodeGen/ARM/tst-peephole.mir
  llvm/test/CodeGen/ARM/vldm-liveness.mir
  llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir
  llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
  llvm/test/CodeGen/Thumb/peephole-cmp.mir
  llvm/test/CodeGen/Thumb/peephole-mi.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/livereg-no-loop-def.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir
  llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir
  llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir
  llvm/test/CodeGen/Thumb2/high-reg-spill.mir
  llvm/test/CodeGen/Thumb2/ifcvt-cbz.mir
  llvm/test/CodeGen/Thumb2/mve-stacksplot.mir
  llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir
  llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir
  llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
  llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir
  llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
  llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
  llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
  llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
  llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
  llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir
  llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir
  llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir
  llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir
  llvm/test/CodeGen/Thumb2/peephole-addsub.mir
  llvm/test/CodeGen/Thumb2/peephole-cmp.mir
  llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir
  llvm/test/CodeGen/Thumb2/t2sizereduction.mir
  llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir

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