[PATCH] D74581: [llvm][CodeGen][aarch64] Add contiguous prefetch intrinsics for SVE.

[Andrzej Warzynski via Phabricator via llvm-commits]

andwar added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:4443
+/// When \p PredVT is a scalable vector predicate in the form
+/// MVT::nx<M>xi1, it builds the correspondent scalable vector of
+/// integers MVT::nx<M>xi<bits> s.t. M x bits = 128. If the input
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[nit] corresponding?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:4491
 
-  EVT MemVT = cast<MemSDNode>(Root)->getMemoryVT();
+  if (MemVT == EVT())
+    return false;
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What's this check for? Wouldn't some hard-coded null-value be more idiomatic?


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Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-contiguous-prefetches.ll:100
+; CHECK-LABEL: test_svprf_vnum_under
+; CHECK-NOT: prfb pstl3strm, p0, [x0, #-33, mul vl]
+entry:
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Would it make sense to add checks for what's expected instead?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D74581/new/

https://reviews.llvm.org/D74581