[PATCH] D68006: DSE miscompile when store is clobbered across loop iterations

[Artur Pilipenko via Phabricator via llvm-commits]

apilipenko updated this revision to Diff 246040.
apilipenko added a comment.

I rework the patch using PHITransAddr. Now instead of tracking the backedge flag I keep track of the address to check and translate the address when needed.

This change should resolve the concern about overly conservative handling of load-store case, when the address dominates all the operations between load and store. Using PHITransAddr we would only do the translation if it's actually needed.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68006/new/

https://reviews.llvm.org/D68006

Files:
  llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
  llvm/test/Transforms/DeadStoreElimination/simple.ll

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