[PATCH] D74937: [AMDGPU] Implement copyPhysReg for 16 bit subregs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

I don't think copies of these should ever be produced (at leasts for the high half) since the high half is not really addressable, and only appears that way to some instructions. Where are copies coming from?



================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:701
+
+    BuildMI(MBB, MI, DL, get(AMDGPU::V_PACK_B32_F16), DestReg)
+      .addImm((!SrcLow && DstLow) ? SISrcMods::OP_SEL_0 : 0) // src0_mods
----------------
V_PACK_B32_F16 has some FP flushing properties and is not suitable for a copy. I think you have to do essentially what D74740 does


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  https://reviews.llvm.org/D74937/new/

https://reviews.llvm.org/D74937