[llvm] d95a10a - [X86] Custom legalize v1i1 add/sub/mul to xor/xor/and with avx512.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 20 15:14:35 PST 2020


Author: Craig Topper
Date: 2020-02-20T15:13:44-08:00
New Revision: d95a10a7f976188e4ffec77d82000afc53a6d39a

URL: https://github.com/llvm/llvm-project/commit/d95a10a7f976188e4ffec77d82000afc53a6d39a
DIFF: https://github.com/llvm/llvm-project/commit/d95a10a7f976188e4ffec77d82000afc53a6d39a.diff

LOG: [X86] Custom legalize v1i1 add/sub/mul to xor/xor/and with avx512.

We already did this for v2i1, v4i1, v8i1, etc.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/avx512-mask-op.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 0388574c0e7b..e31d82442183 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1441,10 +1441,13 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
       setOperationAction(ISD::ANY_EXTEND,  VT, Custom);
     }
 
-    for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
+    for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
       setOperationAction(ISD::ADD,              VT, Custom);
       setOperationAction(ISD::SUB,              VT, Custom);
       setOperationAction(ISD::MUL,              VT, Custom);
+    }
+
+    for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
       setOperationAction(ISD::SETCC,            VT, Custom);
       setOperationAction(ISD::STRICT_FSETCC,    VT, Custom);
       setOperationAction(ISD::STRICT_FSETCCS,   VT, Custom);

diff  --git a/llvm/test/CodeGen/X86/avx512-mask-op.ll b/llvm/test/CodeGen/X86/avx512-mask-op.ll
index ffb2e329cdd5..796d3586310c 100644
--- a/llvm/test/CodeGen/X86/avx512-mask-op.ll
+++ b/llvm/test/CodeGen/X86/avx512-mask-op.ll
@@ -5315,6 +5315,219 @@ define <64 x i1> @mask64_insert(i32 %a) {
   ret <64 x i1> %maskv
 }
 
+define i1 @test_v1i1_add(i1 %x, i1 %y) {
+; KNL-LABEL: test_v1i1_add:
+; KNL:       ## %bb.0:
+; KNL-NEXT:    kmovw %edi, %k0
+; KNL-NEXT:    kmovw %esi, %k1
+; KNL-NEXT:    kxorw %k1, %k0, %k0
+; KNL-NEXT:    kmovw %k0, %eax
+; KNL-NEXT:    movb %al, -{{[0-9]+}}(%rsp)
+; KNL-NEXT:    movb -{{[0-9]+}}(%rsp), %al
+; KNL-NEXT:    retq
+;
+; SKX-LABEL: test_v1i1_add:
+; SKX:       ## %bb.0:
+; SKX-NEXT:    andl $1, %edi
+; SKX-NEXT:    movb %dil, -{{[0-9]+}}(%rsp)
+; SKX-NEXT:    andl $1, %esi
+; SKX-NEXT:    movb %sil, -{{[0-9]+}}(%rsp)
+; SKX-NEXT:    kmovb -{{[0-9]+}}(%rsp), %k0
+; SKX-NEXT:    kmovb -{{[0-9]+}}(%rsp), %k1
+; SKX-NEXT:    kxorw %k1, %k0, %k0
+; SKX-NEXT:    kmovb %k0, -{{[0-9]+}}(%rsp)
+; SKX-NEXT:    movb -{{[0-9]+}}(%rsp), %al
+; SKX-NEXT:    retq
+;
+; AVX512BW-LABEL: test_v1i1_add:
+; AVX512BW:       ## %bb.0:
+; AVX512BW-NEXT:    kmovd %edi, %k0
+; AVX512BW-NEXT:    kmovd %esi, %k1
+; AVX512BW-NEXT:    kxorw %k1, %k0, %k0
+; AVX512BW-NEXT:    kmovd %k0, %eax
+; AVX512BW-NEXT:    movb %al, -{{[0-9]+}}(%rsp)
+; AVX512BW-NEXT:    movb -{{[0-9]+}}(%rsp), %al
+; AVX512BW-NEXT:    retq
+;
+; AVX512DQ-LABEL: test_v1i1_add:
+; AVX512DQ:       ## %bb.0:
+; AVX512DQ-NEXT:    andl $1, %edi
+; AVX512DQ-NEXT:    movb %dil, -{{[0-9]+}}(%rsp)
+; AVX512DQ-NEXT:    andl $1, %esi
+; AVX512DQ-NEXT:    movb %sil, -{{[0-9]+}}(%rsp)
+; AVX512DQ-NEXT:    kmovb -{{[0-9]+}}(%rsp), %k0
+; AVX512DQ-NEXT:    kmovb -{{[0-9]+}}(%rsp), %k1
+; AVX512DQ-NEXT:    kxorw %k1, %k0, %k0
+; AVX512DQ-NEXT:    kmovb %k0, -{{[0-9]+}}(%rsp)
+; AVX512DQ-NEXT:    movb -{{[0-9]+}}(%rsp), %al
+; AVX512DQ-NEXT:    retq
+;
+; X86-LABEL: test_v1i1_add:
+; X86:       ## %bb.0:
+; X86-NEXT:    pushl %eax
+; X86-NEXT:    .cfi_def_cfa_offset 8
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X86-NEXT:    andb $1, %al
+; X86-NEXT:    movb %al, {{[0-9]+}}(%esp)
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X86-NEXT:    andb $1, %al
+; X86-NEXT:    movb %al, {{[0-9]+}}(%esp)
+; X86-NEXT:    kmovb {{[0-9]+}}(%esp), %k0
+; X86-NEXT:    kmovb {{[0-9]+}}(%esp), %k1
+; X86-NEXT:    kxorw %k1, %k0, %k0
+; X86-NEXT:    kmovb %k0, {{[0-9]+}}(%esp)
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X86-NEXT:    popl %ecx
+; X86-NEXT:    retl
+  %m0 = bitcast i1 %x to <1 x i1>
+  %m1 = bitcast i1 %y to <1 x i1>
+  %m2 = add <1 x i1> %m0,  %m1
+  %ret = bitcast <1 x i1> %m2 to i1
+  ret i1 %ret
+}
+
+define i1 @test_v1i1_sub(i1 %x, i1 %y) {
+; KNL-LABEL: test_v1i1_sub:
+; KNL:       ## %bb.0:
+; KNL-NEXT:    kmovw %edi, %k0
+; KNL-NEXT:    kmovw %esi, %k1
+; KNL-NEXT:    kxorw %k1, %k0, %k0
+; KNL-NEXT:    kmovw %k0, %eax
+; KNL-NEXT:    movb %al, -{{[0-9]+}}(%rsp)
+; KNL-NEXT:    movb -{{[0-9]+}}(%rsp), %al
+; KNL-NEXT:    retq
+;
+; SKX-LABEL: test_v1i1_sub:
+; SKX:       ## %bb.0:
+; SKX-NEXT:    andl $1, %edi
+; SKX-NEXT:    movb %dil, -{{[0-9]+}}(%rsp)
+; SKX-NEXT:    andl $1, %esi
+; SKX-NEXT:    movb %sil, -{{[0-9]+}}(%rsp)
+; SKX-NEXT:    kmovb -{{[0-9]+}}(%rsp), %k0
+; SKX-NEXT:    kmovb -{{[0-9]+}}(%rsp), %k1
+; SKX-NEXT:    kxorw %k1, %k0, %k0
+; SKX-NEXT:    kmovb %k0, -{{[0-9]+}}(%rsp)
+; SKX-NEXT:    movb -{{[0-9]+}}(%rsp), %al
+; SKX-NEXT:    retq
+;
+; AVX512BW-LABEL: test_v1i1_sub:
+; AVX512BW:       ## %bb.0:
+; AVX512BW-NEXT:    kmovd %edi, %k0
+; AVX512BW-NEXT:    kmovd %esi, %k1
+; AVX512BW-NEXT:    kxorw %k1, %k0, %k0
+; AVX512BW-NEXT:    kmovd %k0, %eax
+; AVX512BW-NEXT:    movb %al, -{{[0-9]+}}(%rsp)
+; AVX512BW-NEXT:    movb -{{[0-9]+}}(%rsp), %al
+; AVX512BW-NEXT:    retq
+;
+; AVX512DQ-LABEL: test_v1i1_sub:
+; AVX512DQ:       ## %bb.0:
+; AVX512DQ-NEXT:    andl $1, %edi
+; AVX512DQ-NEXT:    movb %dil, -{{[0-9]+}}(%rsp)
+; AVX512DQ-NEXT:    andl $1, %esi
+; AVX512DQ-NEXT:    movb %sil, -{{[0-9]+}}(%rsp)
+; AVX512DQ-NEXT:    kmovb -{{[0-9]+}}(%rsp), %k0
+; AVX512DQ-NEXT:    kmovb -{{[0-9]+}}(%rsp), %k1
+; AVX512DQ-NEXT:    kxorw %k1, %k0, %k0
+; AVX512DQ-NEXT:    kmovb %k0, -{{[0-9]+}}(%rsp)
+; AVX512DQ-NEXT:    movb -{{[0-9]+}}(%rsp), %al
+; AVX512DQ-NEXT:    retq
+;
+; X86-LABEL: test_v1i1_sub:
+; X86:       ## %bb.0:
+; X86-NEXT:    pushl %eax
+; X86-NEXT:    .cfi_def_cfa_offset 8
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X86-NEXT:    andb $1, %al
+; X86-NEXT:    movb %al, {{[0-9]+}}(%esp)
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X86-NEXT:    andb $1, %al
+; X86-NEXT:    movb %al, {{[0-9]+}}(%esp)
+; X86-NEXT:    kmovb {{[0-9]+}}(%esp), %k0
+; X86-NEXT:    kmovb {{[0-9]+}}(%esp), %k1
+; X86-NEXT:    kxorw %k1, %k0, %k0
+; X86-NEXT:    kmovb %k0, {{[0-9]+}}(%esp)
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X86-NEXT:    popl %ecx
+; X86-NEXT:    retl
+  %m0 = bitcast i1 %x to <1 x i1>
+  %m1 = bitcast i1 %y to <1 x i1>
+  %m2 = sub <1 x i1> %m0,  %m1
+  %ret = bitcast <1 x i1> %m2 to i1
+  ret i1 %ret
+}
+
+define i1 @test_v1i1_mul(i1 %x, i1 %y) {
+; KNL-LABEL: test_v1i1_mul:
+; KNL:       ## %bb.0:
+; KNL-NEXT:    kmovw %edi, %k0
+; KNL-NEXT:    kmovw %esi, %k1
+; KNL-NEXT:    kandw %k1, %k0, %k0
+; KNL-NEXT:    kmovw %k0, %eax
+; KNL-NEXT:    movb %al, -{{[0-9]+}}(%rsp)
+; KNL-NEXT:    movb -{{[0-9]+}}(%rsp), %al
+; KNL-NEXT:    retq
+;
+; SKX-LABEL: test_v1i1_mul:
+; SKX:       ## %bb.0:
+; SKX-NEXT:    andl $1, %edi
+; SKX-NEXT:    movb %dil, -{{[0-9]+}}(%rsp)
+; SKX-NEXT:    andl $1, %esi
+; SKX-NEXT:    movb %sil, -{{[0-9]+}}(%rsp)
+; SKX-NEXT:    kmovb -{{[0-9]+}}(%rsp), %k0
+; SKX-NEXT:    kmovb -{{[0-9]+}}(%rsp), %k1
+; SKX-NEXT:    kandw %k1, %k0, %k0
+; SKX-NEXT:    kmovb %k0, -{{[0-9]+}}(%rsp)
+; SKX-NEXT:    movb -{{[0-9]+}}(%rsp), %al
+; SKX-NEXT:    retq
+;
+; AVX512BW-LABEL: test_v1i1_mul:
+; AVX512BW:       ## %bb.0:
+; AVX512BW-NEXT:    kmovd %edi, %k0
+; AVX512BW-NEXT:    kmovd %esi, %k1
+; AVX512BW-NEXT:    kandw %k1, %k0, %k0
+; AVX512BW-NEXT:    kmovd %k0, %eax
+; AVX512BW-NEXT:    movb %al, -{{[0-9]+}}(%rsp)
+; AVX512BW-NEXT:    movb -{{[0-9]+}}(%rsp), %al
+; AVX512BW-NEXT:    retq
+;
+; AVX512DQ-LABEL: test_v1i1_mul:
+; AVX512DQ:       ## %bb.0:
+; AVX512DQ-NEXT:    andl $1, %edi
+; AVX512DQ-NEXT:    movb %dil, -{{[0-9]+}}(%rsp)
+; AVX512DQ-NEXT:    andl $1, %esi
+; AVX512DQ-NEXT:    movb %sil, -{{[0-9]+}}(%rsp)
+; AVX512DQ-NEXT:    kmovb -{{[0-9]+}}(%rsp), %k0
+; AVX512DQ-NEXT:    kmovb -{{[0-9]+}}(%rsp), %k1
+; AVX512DQ-NEXT:    kandw %k1, %k0, %k0
+; AVX512DQ-NEXT:    kmovb %k0, -{{[0-9]+}}(%rsp)
+; AVX512DQ-NEXT:    movb -{{[0-9]+}}(%rsp), %al
+; AVX512DQ-NEXT:    retq
+;
+; X86-LABEL: test_v1i1_mul:
+; X86:       ## %bb.0:
+; X86-NEXT:    pushl %eax
+; X86-NEXT:    .cfi_def_cfa_offset 8
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X86-NEXT:    andb $1, %al
+; X86-NEXT:    movb %al, {{[0-9]+}}(%esp)
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X86-NEXT:    andb $1, %al
+; X86-NEXT:    movb %al, {{[0-9]+}}(%esp)
+; X86-NEXT:    kmovb {{[0-9]+}}(%esp), %k0
+; X86-NEXT:    kmovb {{[0-9]+}}(%esp), %k1
+; X86-NEXT:    kandw %k1, %k0, %k0
+; X86-NEXT:    kmovb %k0, {{[0-9]+}}(%esp)
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X86-NEXT:    popl %ecx
+; X86-NEXT:    retl
+  %m0 = bitcast i1 %x to <1 x i1>
+  %m1 = bitcast i1 %y to <1 x i1>
+  %m2 = mul <1 x i1> %m0,  %m1
+  %ret = bitcast <1 x i1> %m2 to i1
+  ret i1 %ret
+}
+
 !llvm.module.flags = !{!0}
 !0 = !{i32 1, !"ProfileSummary", !1}
 !1 = !{!2, !3, !4, !5, !6, !7, !8, !9}


        


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