[PATCH] D74874: [mlir][spirv] Add lowering for load/store zero-rank memref from std to SPIR-V.

[Han-Chung Wang via Phabricator via llvm-commits]

hanchung added a comment.
Herald added a subscriber: bader.

This might be wrong. Do we expect to load/store f/i32 instead of spv.array<1 x f/i32 [4]>?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D74874/new/

https://reviews.llvm.org/D74874