[PATCH] D74873: [AMDGPU] Define 16 bit VGPR subregs

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
rampitec added a reviewer: arsenm.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

We have loads preserving low and high 16 bits of their
destinations. However, we always use a whole 32 bit register
for these. The same happens with 16 bit stores, we have to
use full 32 bit register so if high bits are clobbered the
register needs to be copied. One example of such code is
added to the load-hi16.ll.

The proper solution to the problem is to define 16 bit subregs
and use them in the operations which do not read another half
of a VGPR or preserve it if the VGPR is written.

This patch simply defines subregisters and register classes.
At the moment there should be no difference in code generation.
A lot more work is needed to actually use these new register
classes. Therefore, there are no new tests at this time.

Register weight calculation has changed with new subregs so
appropriate changes were made to keep all calculations just
as they are now, especially calculations of register pressure.


https://reviews.llvm.org/D74873

Files:
  llvm/include/llvm/MC/LaneBitmask.h
  llvm/lib/CodeGen/MIRParser/MIParser.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
  llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
  llvm/test/CodeGen/AMDGPU/load-hi16.ll
  llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
  llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
  llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir
  llvm/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir

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