[llvm] 4bb0c8f - AMDGPU: Enable integer division bypass
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 19 14:50:33 PST 2020
Author: Matt Arsenault
Date: 2020-02-19T17:50:19-05:00
New Revision: 4bb0c8f91cb7448ef6de913367f2b46b46392fda
URL: https://github.com/llvm/llvm-project/commit/4bb0c8f91cb7448ef6de913367f2b46b46392fda
DIFF: https://github.com/llvm/llvm-project/commit/4bb0c8f91cb7448ef6de913367f2b46b46392fda.diff
LOG: AMDGPU: Enable integer division bypass
We probably want this, and I've meant to turn this on for a long
time. SC actually emits a special case to early-out for a 1
denominator, which perhaps should also be considered.
Added:
llvm/test/CodeGen/AMDGPU/bypass-div.ll
Modified:
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
llvm/test/CodeGen/AMDGPU/sdiv64.ll
llvm/test/CodeGen/AMDGPU/sdivrem64.r600.ll
llvm/test/CodeGen/AMDGPU/srem64.ll
llvm/test/CodeGen/AMDGPU/udiv64.ll
llvm/test/CodeGen/AMDGPU/urem64.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index bbd5c8ef1eb3..8cbe4485db4f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -37,6 +37,11 @@ using namespace llvm;
#include "AMDGPUGenCallingConv.inc"
+static cl::opt<bool> AMDGPUBypassSlowDiv(
+ "amdgpu-bypass-slow-div",
+ cl::desc("Skip 64-bit divide for dynamic 32-bit values"),
+ cl::init(true));
+
// Find a larger type to do a load / store of a vector with.
EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
unsigned StoreSize = VT.getStoreSizeInBits();
@@ -482,6 +487,10 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
MaxStoresPerMemmove = 0xffffffff;
MaxStoresPerMemset = 0xffffffff;
+ // The expansion for 64-bit division is enormous.
+ if (AMDGPUBypassSlowDiv)
+ addBypassSlowDiv(64, 32);
+
setTargetDAGCombine(ISD::BITCAST);
setTargetDAGCombine(ISD::SHL);
setTargetDAGCombine(ISD::SRA);
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
index 0f4c09433c1c..b835365ec0c6 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-codegenprepare %s | FileCheck %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s
+; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-codegenprepare -amdgpu-bypass-slow-div=0 %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-bypass-slow-div=0 < %s | FileCheck -check-prefix=GCN %s
define amdgpu_kernel void @udiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
; CHECK-LABEL: @udiv_i32(
diff --git a/llvm/test/CodeGen/AMDGPU/bypass-div.ll b/llvm/test/CodeGen/AMDGPU/bypass-div.ll
new file mode 100644
index 000000000000..f6672548a94c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/bypass-div.ll
@@ -0,0 +1,1208 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+
+; 64-bit divides and rems should be split into a fast and slow path
+; where the fast path uses a 32-bit operation.
+
+define i64 @sdiv64(i64 %a, i64 %b) {
+; GFX9-LABEL: sdiv64:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v5, v3
+; GFX9-NEXT: v_or_b32_e32 v4, v1, v5
+; GFX9-NEXT: v_mov_b32_e32 v3, 0
+; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[3:4]
+; GFX9-NEXT: ; implicit-def: $vgpr3_vgpr4
+; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execz BB0_2
+; GFX9-NEXT: ; %bb.1:
+; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v5
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v2, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v4, v4, v3
+; GFX9-NEXT: v_xor_b32_e32 v5, v5, v3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v6, v4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v7, v5
+; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, 0, v4
+; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, 0, v5, vcc
+; GFX9-NEXT: v_mov_b32_e32 v16, 0
+; GFX9-NEXT: v_mac_f32_e32 v6, 0x4f800000, v7
+; GFX9-NEXT: v_rcp_f32_e32 v6, v6
+; GFX9-NEXT: v_mov_b32_e32 v15, 0
+; GFX9-NEXT: v_mul_f32_e32 v6, 0x5f7ffffc, v6
+; GFX9-NEXT: v_mul_f32_e32 v7, 0x2f800000, v6
+; GFX9-NEXT: v_trunc_f32_e32 v7, v7
+; GFX9-NEXT: v_mac_f32_e32 v6, 0xcf800000, v7
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX9-NEXT: v_mul_lo_u32 v10, v9, v6
+; GFX9-NEXT: v_mul_hi_u32 v11, v8, v6
+; GFX9-NEXT: v_mul_lo_u32 v12, v8, v7
+; GFX9-NEXT: v_mul_lo_u32 v13, v8, v6
+; GFX9-NEXT: v_add3_u32 v10, v11, v12, v10
+; GFX9-NEXT: v_mul_lo_u32 v12, v6, v10
+; GFX9-NEXT: v_mul_hi_u32 v14, v6, v13
+; GFX9-NEXT: v_mul_hi_u32 v11, v6, v10
+; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v14, v12
+; GFX9-NEXT: v_mul_lo_u32 v14, v7, v13
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v11, vcc
+; GFX9-NEXT: v_mul_hi_u32 v13, v7, v13
+; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v14, v12
+; GFX9-NEXT: v_mul_hi_u32 v12, v7, v10
+; GFX9-NEXT: v_mul_lo_u32 v10, v7, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v11, v13, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, v12, v15, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT: v_add_co_u32_e64 v6, s[4:5], v6, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v10, vcc, v7, v11, s[4:5]
+; GFX9-NEXT: v_mul_lo_u32 v12, v8, v10
+; GFX9-NEXT: v_mul_hi_u32 v13, v8, v6
+; GFX9-NEXT: v_mul_lo_u32 v9, v9, v6
+; GFX9-NEXT: v_mul_lo_u32 v8, v8, v6
+; GFX9-NEXT: v_add_u32_e32 v7, v7, v11
+; GFX9-NEXT: v_add3_u32 v9, v13, v12, v9
+; GFX9-NEXT: v_mul_lo_u32 v12, v6, v9
+; GFX9-NEXT: v_mul_hi_u32 v13, v6, v8
+; GFX9-NEXT: v_mul_hi_u32 v14, v6, v9
+; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v13, v12
+; GFX9-NEXT: v_mul_hi_u32 v13, v10, v8
+; GFX9-NEXT: v_mul_lo_u32 v8, v10, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v14, vcc, v16, v14, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v12
+; GFX9-NEXT: v_mul_hi_u32 v8, v10, v9
+; GFX9-NEXT: v_mul_lo_u32 v9, v10, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, v14, v13, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v8, v15, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v12, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v16, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v7, vcc, v7, v8, s[4:5]
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
+; GFX9-NEXT: v_ashrrev_i32_e32 v8, 31, v1
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v0, v8
+; GFX9-NEXT: v_xor_b32_e32 v9, v9, v8
+; GFX9-NEXT: v_mul_lo_u32 v10, v9, v7
+; GFX9-NEXT: v_mul_hi_u32 v11, v9, v6
+; GFX9-NEXT: v_mul_hi_u32 v12, v9, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v8, vcc
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v8
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
+; GFX9-NEXT: v_mul_lo_u32 v12, v1, v6
+; GFX9-NEXT: v_mul_hi_u32 v6, v1, v6
+; GFX9-NEXT: v_mul_hi_u32 v13, v1, v7
+; GFX9-NEXT: v_mul_lo_u32 v7, v1, v7
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v12, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v11, v6, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v15, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v16, v10, vcc
+; GFX9-NEXT: v_mul_lo_u32 v10, v5, v6
+; GFX9-NEXT: v_mul_lo_u32 v11, v4, v7
+; GFX9-NEXT: v_mul_hi_u32 v12, v4, v6
+; GFX9-NEXT: v_mul_lo_u32 v13, v4, v6
+; GFX9-NEXT: v_add3_u32 v10, v12, v11, v10
+; GFX9-NEXT: v_sub_u32_e32 v11, v1, v10
+; GFX9-NEXT: v_sub_co_u32_e32 v9, vcc, v9, v13
+; GFX9-NEXT: v_subb_co_u32_e64 v11, s[4:5], v11, v5, vcc
+; GFX9-NEXT: v_sub_co_u32_e64 v12, s[4:5], v9, v4
+; GFX9-NEXT: v_subbrev_co_u32_e64 v11, s[4:5], 0, v11, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v11, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v12, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v11, v5
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v13, v12, s[4:5]
+; GFX9-NEXT: v_add_co_u32_e64 v12, s[4:5], 2, v6
+; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v7, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
+; GFX9-NEXT: v_add_co_u32_e64 v14, s[4:5], 1, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v9, v4
+; GFX9-NEXT: v_addc_co_u32_e64 v15, s[4:5], 0, v7, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v5
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v4, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v14, v12, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v15, v13, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX9-NEXT: v_xor_b32_e32 v5, v8, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v11, vcc
+; GFX9-NEXT: v_xor_b32_e32 v3, v4, v5
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v5
+; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v1, v5, vcc
+; GFX9-NEXT: BB0_2: ; %Flow
+; GFX9-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
+; GFX9-NEXT: s_xor_b64 exec, exec, s[6:7]
+; GFX9-NEXT: s_cbranch_execz BB0_4
+; GFX9-NEXT: ; %bb.3:
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v2
+; GFX9-NEXT: v_sub_u32_e32 v5, 0, v3
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_mul_hi_u32 v3, v3, v1
+; GFX9-NEXT: v_add_u32_e32 v4, v1, v3
+; GFX9-NEXT: v_sub_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_mul_hi_u32 v1, v1, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
+; GFX9-NEXT: v_add_u32_e32 v5, -1, v1
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
+; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v2
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v1, v4, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v0, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: BB0_4:
+; GFX9-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX9-NEXT: v_mov_b32_e32 v0, v3
+; GFX9-NEXT: v_mov_b32_e32 v1, v4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %d = sdiv i64 %a, %b
+ ret i64 %d
+}
+
+define i64 @udiv64(i64 %a, i64 %b) {
+; GFX9-LABEL: udiv64:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_or_b32_e32 v5, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execz BB1_2
+; GFX9-NEXT: ; %bb.1:
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3
+; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, 0, v2
+; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v13, 0
+; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
+; GFX9-NEXT: v_rcp_f32_e32 v4, v4
+; GFX9-NEXT: v_mov_b32_e32 v12, 0
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
+; GFX9-NEXT: v_trunc_f32_e32 v5, v5
+; GFX9-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX9-NEXT: v_mul_lo_u32 v9, v7, v4
+; GFX9-NEXT: v_mul_lo_u32 v8, v6, v5
+; GFX9-NEXT: v_mul_hi_u32 v10, v6, v4
+; GFX9-NEXT: v_mul_lo_u32 v11, v6, v4
+; GFX9-NEXT: v_add3_u32 v8, v10, v8, v9
+; GFX9-NEXT: v_mul_hi_u32 v9, v4, v11
+; GFX9-NEXT: v_mul_lo_u32 v10, v4, v8
+; GFX9-NEXT: v_mul_hi_u32 v14, v4, v8
+; GFX9-NEXT: v_mul_hi_u32 v15, v5, v8
+; GFX9-NEXT: v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
+; GFX9-NEXT: v_mul_lo_u32 v14, v5, v11
+; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v14, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
+; GFX9-NEXT: v_add_co_u32_e64 v4, s[4:5], v4, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5]
+; GFX9-NEXT: v_mul_lo_u32 v10, v6, v8
+; GFX9-NEXT: v_mul_hi_u32 v11, v6, v4
+; GFX9-NEXT: v_mul_lo_u32 v7, v7, v4
+; GFX9-NEXT: v_mul_lo_u32 v6, v6, v4
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v9
+; GFX9-NEXT: v_add3_u32 v7, v11, v10, v7
+; GFX9-NEXT: v_mul_lo_u32 v10, v4, v7
+; GFX9-NEXT: v_mul_hi_u32 v11, v4, v6
+; GFX9-NEXT: v_mul_hi_u32 v15, v4, v7
+; GFX9-NEXT: v_mul_hi_u32 v14, v8, v7
+; GFX9-NEXT: v_mul_lo_u32 v7, v8, v7
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT: v_mul_hi_u32 v11, v8, v6
+; GFX9-NEXT: v_mul_lo_u32 v6, v8, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v6, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v9, v1, v5
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v8, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v12, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v13, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v6, v3, v4
+; GFX9-NEXT: v_mul_lo_u32 v7, v2, v5
+; GFX9-NEXT: v_mul_hi_u32 v8, v2, v4
+; GFX9-NEXT: v_mul_lo_u32 v9, v2, v4
+; GFX9-NEXT: v_add3_u32 v6, v8, v7, v6
+; GFX9-NEXT: v_sub_u32_e32 v7, v1, v6
+; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v0, v9
+; GFX9-NEXT: v_subb_co_u32_e64 v7, s[4:5], v7, v3, vcc
+; GFX9-NEXT: v_sub_co_u32_e64 v9, s[4:5], v8, v2
+; GFX9-NEXT: v_subbrev_co_u32_e64 v7, s[4:5], 0, v7, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v3
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v10, v9, s[4:5]
+; GFX9-NEXT: v_add_co_u32_e64 v9, s[4:5], 2, v4
+; GFX9-NEXT: v_addc_co_u32_e64 v10, s[4:5], 0, v5, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
+; GFX9-NEXT: v_add_co_u32_e64 v11, s[4:5], 1, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v8, v2
+; GFX9-NEXT: v_addc_co_u32_e64 v12, s[4:5], 0, v5, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v8, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v12, v10, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v11, v9, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
+; GFX9-NEXT: BB1_2: ; %Flow
+; GFX9-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
+; GFX9-NEXT: s_xor_b64 exec, exec, s[6:7]
+; GFX9-NEXT: s_cbranch_execz BB1_4
+; GFX9-NEXT: ; %bb.3:
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v2
+; GFX9-NEXT: v_sub_u32_e32 v5, 0, v3
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_mul_hi_u32 v3, v3, v1
+; GFX9-NEXT: v_add_u32_e32 v4, v1, v3
+; GFX9-NEXT: v_sub_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_mul_hi_u32 v1, v1, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
+; GFX9-NEXT: v_add_u32_e32 v5, -1, v1
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
+; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v2
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v1, v4, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v0, vcc
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: BB1_4:
+; GFX9-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: v_mov_b32_e32 v1, v5
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %d = udiv i64 %a, %b
+ ret i64 %d
+}
+
+define i64 @srem64(i64 %a, i64 %b) {
+; GFX9-LABEL: srem64:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v5, v3
+; GFX9-NEXT: v_or_b32_e32 v4, v1, v5
+; GFX9-NEXT: v_mov_b32_e32 v3, 0
+; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[3:4]
+; GFX9-NEXT: ; implicit-def: $vgpr3_vgpr4
+; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX9-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execz BB2_2
+; GFX9-NEXT: ; %bb.1:
+; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v5
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v2, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v5, v5, v3
+; GFX9-NEXT: v_xor_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v6, v5
+; GFX9-NEXT: v_sub_co_u32_e32 v7, vcc, 0, v3
+; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, 0, v5, vcc
+; GFX9-NEXT: v_mov_b32_e32 v15, 0
+; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
+; GFX9-NEXT: v_rcp_f32_e32 v4, v4
+; GFX9-NEXT: v_mov_b32_e32 v14, 0
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GFX9-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4
+; GFX9-NEXT: v_trunc_f32_e32 v6, v6
+; GFX9-NEXT: v_mac_f32_e32 v4, 0xcf800000, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT: v_mul_lo_u32 v9, v8, v4
+; GFX9-NEXT: v_mul_hi_u32 v10, v7, v4
+; GFX9-NEXT: v_mul_lo_u32 v11, v7, v6
+; GFX9-NEXT: v_mul_lo_u32 v12, v7, v4
+; GFX9-NEXT: v_add3_u32 v9, v10, v11, v9
+; GFX9-NEXT: v_mul_lo_u32 v11, v4, v9
+; GFX9-NEXT: v_mul_hi_u32 v13, v4, v12
+; GFX9-NEXT: v_mul_hi_u32 v10, v4, v9
+; GFX9-NEXT: v_mul_hi_u32 v16, v6, v9
+; GFX9-NEXT: v_mul_lo_u32 v9, v6, v9
+; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v13, v11
+; GFX9-NEXT: v_mul_lo_u32 v13, v6, v12
+; GFX9-NEXT: v_mul_hi_u32 v12, v6, v12
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v10, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v13, v11
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v14, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
+; GFX9-NEXT: v_add_co_u32_e64 v4, s[4:5], v4, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5]
+; GFX9-NEXT: v_mul_lo_u32 v11, v7, v9
+; GFX9-NEXT: v_mul_hi_u32 v12, v7, v4
+; GFX9-NEXT: v_mul_lo_u32 v8, v8, v4
+; GFX9-NEXT: v_mul_lo_u32 v7, v7, v4
+; GFX9-NEXT: v_add_u32_e32 v6, v6, v10
+; GFX9-NEXT: v_add3_u32 v8, v12, v11, v8
+; GFX9-NEXT: v_mul_lo_u32 v11, v4, v8
+; GFX9-NEXT: v_mul_hi_u32 v12, v4, v7
+; GFX9-NEXT: v_mul_hi_u32 v16, v4, v8
+; GFX9-NEXT: v_mul_hi_u32 v13, v9, v8
+; GFX9-NEXT: v_mul_lo_u32 v8, v9, v8
+; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11
+; GFX9-NEXT: v_mul_hi_u32 v12, v9, v7
+; GFX9-NEXT: v_mul_lo_u32 v7, v9, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v16, vcc, v15, v16, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v11
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v16, v12, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v13, v14, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v15, v9, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5]
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
+; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v1
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v0, v7
+; GFX9-NEXT: v_xor_b32_e32 v8, v8, v7
+; GFX9-NEXT: v_mul_lo_u32 v9, v8, v6
+; GFX9-NEXT: v_mul_hi_u32 v10, v8, v4
+; GFX9-NEXT: v_mul_hi_u32 v11, v8, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v7, vcc
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v7
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
+; GFX9-NEXT: v_mul_lo_u32 v11, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v12, v1, v6
+; GFX9-NEXT: v_mul_lo_u32 v6, v1, v6
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v11, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v10, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v12, v14, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v15, v9, vcc
+; GFX9-NEXT: v_mul_lo_u32 v9, v5, v4
+; GFX9-NEXT: v_mul_hi_u32 v10, v3, v4
+; GFX9-NEXT: v_mul_lo_u32 v6, v3, v6
+; GFX9-NEXT: v_mul_lo_u32 v4, v3, v4
+; GFX9-NEXT: v_add3_u32 v6, v10, v6, v9
+; GFX9-NEXT: v_sub_u32_e32 v9, v1, v6
+; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v8, v4
+; GFX9-NEXT: v_subb_co_u32_e64 v8, s[4:5], v9, v5, vcc
+; GFX9-NEXT: v_sub_co_u32_e64 v9, s[4:5], v4, v3
+; GFX9-NEXT: v_subb_co_u32_e64 v10, s[6:7], v8, v5, s[4:5]
+; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[4:5], 0, v8, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v5
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v5
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[4:5]
+; GFX9-NEXT: v_sub_co_u32_e64 v12, s[4:5], v9, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v4, v3
+; GFX9-NEXT: v_subbrev_co_u32_e64 v10, s[4:5], 0, v10, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v11
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v9, v12, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, v10, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
+; GFX9-NEXT: v_xor_b32_e32 v3, v3, v7
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v7
+; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, v3, v7
+; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v1, v7, vcc
+; GFX9-NEXT: BB2_2: ; %Flow
+; GFX9-NEXT: s_or_saveexec_b64 s[6:7], s[8:9]
+; GFX9-NEXT: s_xor_b64 exec, exec, s[6:7]
+; GFX9-NEXT: s_cbranch_execz BB2_4
+; GFX9-NEXT: ; %bb.3:
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v2
+; GFX9-NEXT: v_sub_u32_e32 v5, 0, v3
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_mul_hi_u32 v3, v3, v1
+; GFX9-NEXT: v_add_u32_e32 v4, v1, v3
+; GFX9-NEXT: v_sub_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_mul_hi_u32 v1, v1, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, v2
+; GFX9-NEXT: v_sub_u32_e32 v3, v0, v1
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v2
+; GFX9-NEXT: v_sub_u32_e32 v0, v3, v2
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], vcc
+; GFX9-NEXT: v_add_u32_e32 v4, v3, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v0, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: BB2_4:
+; GFX9-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX9-NEXT: v_mov_b32_e32 v0, v3
+; GFX9-NEXT: v_mov_b32_e32 v1, v4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %d = srem i64 %a, %b
+ ret i64 %d
+}
+
+define i64 @urem64(i64 %a, i64 %b) {
+; GFX9-LABEL: urem64:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_or_b32_e32 v5, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX9-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execz BB3_2
+; GFX9-NEXT: ; %bb.1:
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3
+; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, 0, v2
+; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v13, 0
+; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
+; GFX9-NEXT: v_rcp_f32_e32 v4, v4
+; GFX9-NEXT: v_mov_b32_e32 v12, 0
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
+; GFX9-NEXT: v_trunc_f32_e32 v5, v5
+; GFX9-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX9-NEXT: v_mul_lo_u32 v9, v7, v4
+; GFX9-NEXT: v_mul_lo_u32 v8, v6, v5
+; GFX9-NEXT: v_mul_hi_u32 v10, v6, v4
+; GFX9-NEXT: v_mul_lo_u32 v11, v6, v4
+; GFX9-NEXT: v_add3_u32 v8, v10, v8, v9
+; GFX9-NEXT: v_mul_hi_u32 v9, v4, v11
+; GFX9-NEXT: v_mul_lo_u32 v10, v4, v8
+; GFX9-NEXT: v_mul_hi_u32 v14, v4, v8
+; GFX9-NEXT: v_mul_hi_u32 v15, v5, v8
+; GFX9-NEXT: v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
+; GFX9-NEXT: v_mul_lo_u32 v14, v5, v11
+; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v14, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
+; GFX9-NEXT: v_add_co_u32_e64 v4, s[4:5], v4, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5]
+; GFX9-NEXT: v_mul_lo_u32 v10, v6, v8
+; GFX9-NEXT: v_mul_hi_u32 v11, v6, v4
+; GFX9-NEXT: v_mul_lo_u32 v7, v7, v4
+; GFX9-NEXT: v_mul_lo_u32 v6, v6, v4
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v9
+; GFX9-NEXT: v_add3_u32 v7, v11, v10, v7
+; GFX9-NEXT: v_mul_lo_u32 v10, v4, v7
+; GFX9-NEXT: v_mul_hi_u32 v11, v4, v6
+; GFX9-NEXT: v_mul_hi_u32 v15, v4, v7
+; GFX9-NEXT: v_mul_hi_u32 v14, v8, v7
+; GFX9-NEXT: v_mul_lo_u32 v7, v8, v7
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT: v_mul_hi_u32 v11, v8, v6
+; GFX9-NEXT: v_mul_lo_u32 v6, v8, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v6, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v9, v1, v5
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v8, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v12, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v13, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v6, v3, v4
+; GFX9-NEXT: v_mul_hi_u32 v7, v2, v4
+; GFX9-NEXT: v_mul_lo_u32 v5, v2, v5
+; GFX9-NEXT: v_mul_lo_u32 v4, v2, v4
+; GFX9-NEXT: v_add3_u32 v5, v7, v5, v6
+; GFX9-NEXT: v_sub_u32_e32 v6, v1, v5
+; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v4
+; GFX9-NEXT: v_subb_co_u32_e64 v6, s[4:5], v6, v3, vcc
+; GFX9-NEXT: v_sub_co_u32_e64 v7, s[4:5], v4, v2
+; GFX9-NEXT: v_subb_co_u32_e64 v8, s[6:7], v6, v3, s[4:5]
+; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[4:5], 0, v6, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v6, v3
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v9, v10, s[4:5]
+; GFX9-NEXT: v_sub_co_u32_e64 v10, s[4:5], v7, v2
+; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[4:5], 0, v8, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v8, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v7, v10, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
+; GFX9-NEXT: BB3_2: ; %Flow
+; GFX9-NEXT: s_or_saveexec_b64 s[6:7], s[8:9]
+; GFX9-NEXT: s_xor_b64 exec, exec, s[6:7]
+; GFX9-NEXT: s_cbranch_execz BB3_4
+; GFX9-NEXT: ; %bb.3:
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v2
+; GFX9-NEXT: v_sub_u32_e32 v5, 0, v3
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_mul_hi_u32 v3, v3, v1
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_add_u32_e32 v4, v1, v3
+; GFX9-NEXT: v_sub_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_mul_hi_u32 v1, v1, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, v2
+; GFX9-NEXT: v_sub_u32_e32 v3, v0, v1
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v2
+; GFX9-NEXT: v_sub_u32_e32 v0, v3, v2
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], vcc
+; GFX9-NEXT: v_add_u32_e32 v4, v3, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
+; GFX9-NEXT: BB3_4:
+; GFX9-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: v_mov_b32_e32 v1, v5
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %d = urem i64 %a, %b
+ ret i64 %d
+}
+
+define i32 @sdiv32(i32 %a, i32 %b) {
+; GFX9-LABEL: sdiv32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v2
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v1
+; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v0
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v4
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v4
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX9-NEXT: v_xor_b32_e32 v2, v4, v2
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f800000, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, v3, v1
+; GFX9-NEXT: v_mul_hi_u32 v5, v3, v1
+; GFX9-NEXT: v_sub_u32_e32 v6, 0, v4
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_mul_hi_u32 v4, v4, v3
+; GFX9-NEXT: v_add_u32_e32 v5, v3, v4
+; GFX9-NEXT: v_sub_u32_e32 v3, v3, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_mul_hi_u32 v3, v3, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, v3, v1
+; GFX9-NEXT: v_add_u32_e32 v5, 1, v3
+; GFX9-NEXT: v_add_u32_e32 v6, -1, v3
+; GFX9-NEXT: v_sub_u32_e32 v7, v0, v4
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v1
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, v5, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_sub_u32_e32 v0, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %d = sdiv i32 %a, %b
+ ret i32 %d
+}
+
+define i32 @udiv32(i32 %a, i32 %b) {
+; GFX9-LABEL: udiv32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v1
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_mul_lo_u32 v3, v2, v1
+; GFX9-NEXT: v_mul_hi_u32 v4, v2, v1
+; GFX9-NEXT: v_sub_u32_e32 v5, 0, v3
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_mul_hi_u32 v3, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v4, v2, v3
+; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX9-NEXT: v_mul_hi_u32 v2, v2, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, v2, v1
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v2
+; GFX9-NEXT: v_add_u32_e32 v5, -1, v2
+; GFX9-NEXT: v_sub_u32_e32 v6, v0, v3
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v1
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %d = udiv i32 %a, %b
+ ret i32 %d
+}
+
+define i32 @srem32(i32 %a, i32 %b) {
+; GFX9-LABEL: srem32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v2
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v1
+; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_mul_lo_u32 v4, v2, v1
+; GFX9-NEXT: v_mul_hi_u32 v5, v2, v1
+; GFX9-NEXT: v_sub_u32_e32 v6, 0, v4
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_mul_hi_u32 v4, v4, v2
+; GFX9-NEXT: v_add_u32_e32 v5, v2, v4
+; GFX9-NEXT: v_sub_u32_e32 v2, v2, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX9-NEXT: v_mul_hi_u32 v2, v2, v0
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, v1
+; GFX9-NEXT: v_sub_u32_e32 v4, v0, v2
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v2
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v4, v1
+; GFX9-NEXT: v_sub_u32_e32 v0, v4, v1
+; GFX9-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX9-NEXT: v_add_u32_e32 v5, v4, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v5, v0, s[4:5]
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v3
+; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %d = srem i32 %a, %b
+ ret i32 %d
+}
+
+define i32 @urem32(i32 %a, i32 %b) {
+; GFX9-LABEL: urem32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v1
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_mul_lo_u32 v3, v2, v1
+; GFX9-NEXT: v_mul_hi_u32 v4, v2, v1
+; GFX9-NEXT: v_sub_u32_e32 v5, 0, v3
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_mul_hi_u32 v3, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v4, v2, v3
+; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX9-NEXT: v_mul_hi_u32 v2, v2, v0
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, v1
+; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v2
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1
+; GFX9-NEXT: v_sub_u32_e32 v0, v3, v1
+; GFX9-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX9-NEXT: v_add_u32_e32 v4, v3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %d = urem i32 %a, %b
+ ret i32 %d
+}
+
+define <2 x i64> @sdivrem64(i64 %a, i64 %b) {
+; GFX9-LABEL: sdivrem64:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v7, v3
+; GFX9-NEXT: v_or_b32_e32 v4, v1, v7
+; GFX9-NEXT: v_mov_b32_e32 v3, 0
+; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[3:4]
+; GFX9-NEXT: ; implicit-def: $vgpr5_vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr3_vgpr4
+; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX9-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execz BB8_2
+; GFX9-NEXT: ; %bb.1:
+; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v7
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v2, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v6, v4, v3
+; GFX9-NEXT: v_xor_b32_e32 v5, v5, v3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v6
+; GFX9-NEXT: v_cvt_f32_u32_e32 v7, v5
+; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, 0, v6
+; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, 0, v5, vcc
+; GFX9-NEXT: v_mov_b32_e32 v16, 0
+; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v7
+; GFX9-NEXT: v_rcp_f32_e32 v4, v4
+; GFX9-NEXT: v_mov_b32_e32 v15, 0
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GFX9-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4
+; GFX9-NEXT: v_trunc_f32_e32 v7, v7
+; GFX9-NEXT: v_mac_f32_e32 v4, 0xcf800000, v7
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX9-NEXT: v_mul_lo_u32 v10, v9, v4
+; GFX9-NEXT: v_mul_hi_u32 v11, v8, v4
+; GFX9-NEXT: v_mul_lo_u32 v12, v8, v7
+; GFX9-NEXT: v_mul_lo_u32 v13, v8, v4
+; GFX9-NEXT: v_add3_u32 v10, v11, v12, v10
+; GFX9-NEXT: v_mul_lo_u32 v12, v4, v10
+; GFX9-NEXT: v_mul_hi_u32 v14, v4, v13
+; GFX9-NEXT: v_mul_hi_u32 v11, v4, v10
+; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v14, v12
+; GFX9-NEXT: v_mul_lo_u32 v14, v7, v13
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v11, vcc
+; GFX9-NEXT: v_mul_hi_u32 v13, v7, v13
+; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v14, v12
+; GFX9-NEXT: v_mul_hi_u32 v12, v7, v10
+; GFX9-NEXT: v_mul_lo_u32 v10, v7, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v11, v13, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, v12, v15, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT: v_add_co_u32_e64 v4, s[4:5], v4, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v10, vcc, v7, v11, s[4:5]
+; GFX9-NEXT: v_mul_lo_u32 v12, v8, v10
+; GFX9-NEXT: v_mul_hi_u32 v13, v8, v4
+; GFX9-NEXT: v_mul_lo_u32 v9, v9, v4
+; GFX9-NEXT: v_mul_lo_u32 v8, v8, v4
+; GFX9-NEXT: v_add_u32_e32 v7, v7, v11
+; GFX9-NEXT: v_add3_u32 v9, v13, v12, v9
+; GFX9-NEXT: v_mul_lo_u32 v12, v4, v9
+; GFX9-NEXT: v_mul_hi_u32 v13, v4, v8
+; GFX9-NEXT: v_mul_hi_u32 v14, v4, v9
+; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v13, v12
+; GFX9-NEXT: v_mul_hi_u32 v13, v10, v8
+; GFX9-NEXT: v_mul_lo_u32 v8, v10, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v14, vcc, v16, v14, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v12
+; GFX9-NEXT: v_mul_hi_u32 v8, v10, v9
+; GFX9-NEXT: v_mul_lo_u32 v9, v10, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, v14, v13, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v8, v15, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v12, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v16, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v7, vcc, v7, v8, s[4:5]
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
+; GFX9-NEXT: v_ashrrev_i32_e32 v8, 31, v1
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v0, v8
+; GFX9-NEXT: v_xor_b32_e32 v9, v9, v8
+; GFX9-NEXT: v_mul_lo_u32 v10, v9, v7
+; GFX9-NEXT: v_mul_hi_u32 v11, v9, v4
+; GFX9-NEXT: v_mul_hi_u32 v12, v9, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v8, vcc
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v8
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
+; GFX9-NEXT: v_mul_lo_u32 v12, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v13, v1, v7
+; GFX9-NEXT: v_mul_lo_u32 v7, v1, v7
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v12, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v11, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v15, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v16, v10, vcc
+; GFX9-NEXT: v_mul_lo_u32 v10, v5, v4
+; GFX9-NEXT: v_mul_lo_u32 v11, v6, v7
+; GFX9-NEXT: v_mul_hi_u32 v12, v6, v4
+; GFX9-NEXT: v_mul_lo_u32 v13, v6, v4
+; GFX9-NEXT: v_add3_u32 v10, v12, v11, v10
+; GFX9-NEXT: v_sub_u32_e32 v11, v1, v10
+; GFX9-NEXT: v_sub_co_u32_e32 v9, vcc, v9, v13
+; GFX9-NEXT: v_subb_co_u32_e64 v11, s[4:5], v11, v5, vcc
+; GFX9-NEXT: v_sub_co_u32_e64 v12, s[4:5], v9, v6
+; GFX9-NEXT: v_subb_co_u32_e64 v13, s[6:7], v11, v5, s[4:5]
+; GFX9-NEXT: v_subbrev_co_u32_e64 v11, s[4:5], 0, v11, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v11, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v12, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v15, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v11, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v14, v14, v15, s[4:5]
+; GFX9-NEXT: v_add_co_u32_e64 v15, s[4:5], 2, v4
+; GFX9-NEXT: v_addc_co_u32_e64 v16, s[4:5], 0, v7, s[4:5]
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v10, vcc
+; GFX9-NEXT: v_add_co_u32_e64 v17, s[4:5], 1, v4
+; GFX9-NEXT: v_addc_co_u32_e64 v18, s[4:5], 0, v7, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v14
+; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v9, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v14, v18, v16, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v16, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v10, v16, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v14, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v17, v15, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX9-NEXT: v_xor_b32_e32 v7, v8, v3
+; GFX9-NEXT: v_xor_b32_e32 v3, v4, v7
+; GFX9-NEXT: v_xor_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_sub_co_u32_e64 v3, s[6:7], v3, v7
+; GFX9-NEXT: v_subb_co_u32_e64 v4, s[6:7], v5, v7, s[6:7]
+; GFX9-NEXT: v_sub_co_u32_e64 v5, s[6:7], v12, v6
+; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[6:7], 0, v13, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v12, v5, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v11, v6, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; GFX9-NEXT: v_xor_b32_e32 v5, v5, v8
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v8
+; GFX9-NEXT: v_sub_co_u32_e32 v5, vcc, v5, v8
+; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v1, v8, vcc
+; GFX9-NEXT: BB8_2: ; %Flow
+; GFX9-NEXT: s_or_saveexec_b64 s[6:7], s[8:9]
+; GFX9-NEXT: s_xor_b64 exec, exec, s[6:7]
+; GFX9-NEXT: s_cbranch_execz BB8_4
+; GFX9-NEXT: ; %bb.3:
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v2
+; GFX9-NEXT: v_sub_u32_e32 v5, 0, v3
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_mul_hi_u32 v3, v3, v1
+; GFX9-NEXT: v_add_u32_e32 v4, v1, v3
+; GFX9-NEXT: v_sub_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_mul_hi_u32 v1, v1, v0
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v1
+; GFX9-NEXT: v_add_u32_e32 v7, -1, v1
+; GFX9-NEXT: v_sub_u32_e32 v5, v0, v3
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v2
+; GFX9-NEXT: v_sub_u32_e32 v0, v5, v2
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], vcc
+; GFX9-NEXT: v_add_u32_e32 v8, v5, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v5, v0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v8, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v1, v6, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v0, vcc
+; GFX9-NEXT: v_mov_b32_e32 v6, v4
+; GFX9-NEXT: BB8_4:
+; GFX9-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX9-NEXT: v_mov_b32_e32 v0, v3
+; GFX9-NEXT: v_mov_b32_e32 v1, v4
+; GFX9-NEXT: v_mov_b32_e32 v2, v5
+; GFX9-NEXT: v_mov_b32_e32 v3, v6
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %d = sdiv i64 %a, %b
+ %r = srem i64 %a, %b
+ %ins.0 = insertelement <2 x i64> undef, i64 %d, i32 0
+ %ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1
+ ret <2 x i64> %ins.1
+}
+
+define <2 x i64> @udivrem64(i64 %a, i64 %b) {
+; GFX9-LABEL: udivrem64:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_or_b32_e32 v5, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX9-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX9-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execz BB9_2
+; GFX9-NEXT: ; %bb.1:
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3
+; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, 0, v2
+; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v13, 0
+; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
+; GFX9-NEXT: v_rcp_f32_e32 v4, v4
+; GFX9-NEXT: v_mov_b32_e32 v12, 0
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
+; GFX9-NEXT: v_trunc_f32_e32 v5, v5
+; GFX9-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX9-NEXT: v_mul_lo_u32 v9, v7, v4
+; GFX9-NEXT: v_mul_lo_u32 v8, v6, v5
+; GFX9-NEXT: v_mul_hi_u32 v10, v6, v4
+; GFX9-NEXT: v_mul_lo_u32 v11, v6, v4
+; GFX9-NEXT: v_add3_u32 v8, v10, v8, v9
+; GFX9-NEXT: v_mul_hi_u32 v9, v4, v11
+; GFX9-NEXT: v_mul_lo_u32 v10, v4, v8
+; GFX9-NEXT: v_mul_hi_u32 v14, v4, v8
+; GFX9-NEXT: v_mul_hi_u32 v15, v5, v8
+; GFX9-NEXT: v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
+; GFX9-NEXT: v_mul_lo_u32 v14, v5, v11
+; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v14, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
+; GFX9-NEXT: v_add_co_u32_e64 v4, s[4:5], v4, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5]
+; GFX9-NEXT: v_mul_lo_u32 v10, v6, v8
+; GFX9-NEXT: v_mul_hi_u32 v11, v6, v4
+; GFX9-NEXT: v_mul_lo_u32 v7, v7, v4
+; GFX9-NEXT: v_mul_lo_u32 v6, v6, v4
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v9
+; GFX9-NEXT: v_add3_u32 v7, v11, v10, v7
+; GFX9-NEXT: v_mul_lo_u32 v10, v4, v7
+; GFX9-NEXT: v_mul_hi_u32 v11, v4, v6
+; GFX9-NEXT: v_mul_hi_u32 v15, v4, v7
+; GFX9-NEXT: v_mul_hi_u32 v14, v8, v7
+; GFX9-NEXT: v_mul_lo_u32 v7, v8, v7
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT: v_mul_hi_u32 v11, v8, v6
+; GFX9-NEXT: v_mul_lo_u32 v6, v8, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v6, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v9, v1, v5
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v8, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v12, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v13, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v6, v3, v4
+; GFX9-NEXT: v_mul_lo_u32 v7, v2, v5
+; GFX9-NEXT: v_mul_hi_u32 v8, v2, v4
+; GFX9-NEXT: v_mul_lo_u32 v9, v2, v4
+; GFX9-NEXT: v_add3_u32 v6, v8, v7, v6
+; GFX9-NEXT: v_sub_u32_e32 v7, v1, v6
+; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v0, v9
+; GFX9-NEXT: v_subb_co_u32_e64 v7, s[4:5], v7, v3, vcc
+; GFX9-NEXT: v_sub_co_u32_e64 v9, s[4:5], v8, v2
+; GFX9-NEXT: v_subb_co_u32_e64 v10, s[6:7], v7, v3, s[4:5]
+; GFX9-NEXT: v_subbrev_co_u32_e64 v7, s[4:5], 0, v7, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[4:5]
+; GFX9-NEXT: v_add_co_u32_e64 v12, s[4:5], 2, v4
+; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v5, s[4:5]
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e64 v14, s[4:5], 1, v4
+; GFX9-NEXT: v_addc_co_u32_e64 v15, s[4:5], 0, v5, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v11
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v8, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v15, v13, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v6, v13, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v14, v12, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v3, vcc
+; GFX9-NEXT: v_sub_co_u32_e64 v3, s[6:7], v9, v2
+; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[6:7], 0, v10, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v7, v6, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v1, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v9, v3, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v8, v1, vcc
+; GFX9-NEXT: BB9_2: ; %Flow
+; GFX9-NEXT: s_or_saveexec_b64 s[6:7], s[8:9]
+; GFX9-NEXT: s_xor_b64 exec, exec, s[6:7]
+; GFX9-NEXT: s_cbranch_execz BB9_4
+; GFX9-NEXT: ; %bb.3:
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v2
+; GFX9-NEXT: v_sub_u32_e32 v5, 0, v3
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_mul_hi_u32 v3, v3, v1
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_add_u32_e32 v4, v1, v3
+; GFX9-NEXT: v_sub_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_mul_hi_u32 v1, v1, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
+; GFX9-NEXT: v_add_u32_e32 v7, -1, v1
+; GFX9-NEXT: v_sub_u32_e32 v6, v0, v3
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v2
+; GFX9-NEXT: v_sub_u32_e32 v0, v6, v2
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], vcc
+; GFX9-NEXT: v_add_u32_e32 v8, v6, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, v0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v8, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v1, v4, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v7, v0, vcc
+; GFX9-NEXT: v_mov_b32_e32 v7, v5
+; GFX9-NEXT: BB9_4:
+; GFX9-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: v_mov_b32_e32 v1, v5
+; GFX9-NEXT: v_mov_b32_e32 v2, v6
+; GFX9-NEXT: v_mov_b32_e32 v3, v7
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %d = udiv i64 %a, %b
+ %r = urem i64 %a, %b
+ %ins.0 = insertelement <2 x i64> undef, i64 %d, i32 0
+ %ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1
+ ret <2 x i64> %ins.1
+}
+
+define i64 @sdiv64_known32(i64 %a, i64 %b) {
+; GFX9-LABEL: sdiv64_known32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_trunc_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %a.ext = ashr i64 %a, 32
+ %b.ext = ashr i64 %b, 32
+ %d = udiv i64 %a.ext, %b.ext
+ ret i64 %d
+}
+
+define i64 @udiv64_known32(i64 %a, i64 %b) {
+; GFX9-LABEL: udiv64_known32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v1
+; GFX9-NEXT: v_mul_f32_e32 v2, v0, v2
+; GFX9-NEXT: v_trunc_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX9-NEXT: v_mad_f32 v0, -v2, v1, v0
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %a.mask = and i64 %a, 4294967295
+ %b.mask = and i64 %b, 4294967295
+ %d = udiv i64 %a.mask, %b.mask
+ ret i64 %d
+}
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
index c64547d1882b..1a6059a0eb86 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
+; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_sdiv:
diff --git a/llvm/test/CodeGen/AMDGPU/sdivrem64.r600.ll b/llvm/test/CodeGen/AMDGPU/sdivrem64.r600.ll
index db6621da8843..2cdfb06268e4 100644
--- a/llvm/test/CodeGen/AMDGPU/sdivrem64.r600.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdivrem64.r600.ll
@@ -1,4 +1,4 @@
-;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s
+;RUN: llc -march=r600 -mcpu=redwood -amdgpu-bypass-slow-div=0 < %s | FileCheck -check-prefix=EG %s
;EG-LABEL: {{^}}s_test_sdiv:
;EG: RECIP_UINT
diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll
index 6cdb5370fd85..1a4ef205cb1c 100644
--- a/llvm/test/CodeGen/AMDGPU/srem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem64.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
+; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_srem:
diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll
index 7fb46f48e41c..a545b756fae0 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
+; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_udiv_i64:
diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll
index 773e65d5a4e8..9a9703c3803c 100644
--- a/llvm/test/CodeGen/AMDGPU/urem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/urem64.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
+; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_urem_i64:
More information about the llvm-commits
mailing list