[llvm] 8e760e1 - [TBLGEN] Inhibit generation of unneeded psets
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 17 15:49:40 PST 2020
Author: Stanislav Mekhanoshin
Date: 2020-02-17T15:38:08-08:00
New Revision: 8e760e1018d1f394661a1d58fcc8dcd303353cae
URL: https://github.com/llvm/llvm-project/commit/8e760e1018d1f394661a1d58fcc8dcd303353cae
DIFF: https://github.com/llvm/llvm-project/commit/8e760e1018d1f394661a1d58fcc8dcd303353cae.diff
LOG: [TBLGEN] Inhibit generation of unneeded psets
Differential Revision: https://reviews.llvm.org/D74744
Added:
llvm/test/TableGen/inhibit-pset.td
Modified:
llvm/include/llvm/Target/Target.td
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/utils/TableGen/CodeGenRegisters.cpp
llvm/utils/TableGen/CodeGenRegisters.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 38abbcebfdf5..c955d5571c05 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -276,6 +276,10 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
// constrained classes first. The value has to be in the range [0,63].
int AllocationPriority = 0;
+ // Generate register pressure set for this register class and any class
+ // synthesized from it. Set to 0 to inhibit unneeded pressure sets.
+ bit GeneratePressureSet = 1;
+
// Weight override for register pressure calculation. This is the value
// TargetRegisterClass::getRegClassWeight() will return. The weight is in
// units of pressure for this register class. If unset tablegen will
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index 927cf6eafb52..861a4f39d511 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -247,6 +247,7 @@ def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
// Give all SGPR classes higher priority than VGPR classes, because
// we want to spill SGPRs to VGPRs.
let AllocationPriority = 9;
+ let GeneratePressureSet = 0;
}
// SGPR 64-bit registers
@@ -443,6 +444,7 @@ def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32], 32,
let CopyCost = -1;
}
+let GeneratePressureSet = 0 in {
// Subset of SReg_32 without M0 for SMRD instructions and alike.
// See comments in SIInstructions.td for more info.
def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
@@ -462,6 +464,7 @@ def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1]
(add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> {
let AllocationPriority = 10;
}
+} // End GeneratePressureSet = 0
// Register class for all scalar registers (SGPRs + Special Registers)
def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
@@ -469,6 +472,7 @@ def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32
let AllocationPriority = 10;
}
+let GeneratePressureSet = 0 in {
def SRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add SReg_32, LDS_DIRECT_CLASS)> {
let isAllocatable = 0;
@@ -696,7 +700,7 @@ def AReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
let CopyCost = 65;
let AllocationPriority = 8;
}
-
+} // End GeneratePressureSet = 0
// This is not a real register. This is just to have a register to add
// to VReg_1 that does not alias any real register that would
@@ -705,6 +709,7 @@ def ARTIFICIAL_VGPR : SIReg <"invalid vgpr", 0> {
let isArtificial = 1;
}
+let GeneratePressureSet = 0 in {
// FIXME: Should specify an empty set for this. No register should
// ever be allocated using VReg_1. This is a hack for SelectionDAG
// that should always be lowered by SILowerI1Copies. TableGen crashes
@@ -733,6 +738,7 @@ def AV_64 : RegisterClass<"AMDGPU", [i64, f64, v4f16], 32,
(add AReg_64, VReg_64)> {
let isAllocatable = 0;
}
+} // End GeneratePressureSet = 0
//===----------------------------------------------------------------------===//
// Register operands
diff --git a/llvm/test/TableGen/inhibit-pset.td b/llvm/test/TableGen/inhibit-pset.td
new file mode 100644
index 000000000000..d9f56137db7a
--- /dev/null
+++ b/llvm/test/TableGen/inhibit-pset.td
@@ -0,0 +1,33 @@
+// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+
+include "reg-with-subregs-common.td"
+
+// CHECK-DAG: GPR32_AND_XR32RegClassID =
+// CHECK-DAG: XR32RegClassID =
+
+def X0 : Register <"x0">;
+
+// CHECK-LABEL: getRegPressureSetName(unsigned Idx) const {
+// CHECK-NEXT: static const char *const PressureNameTable[] = {
+// CHECK-NEXT: "GPR32",
+// CHECK-NEXT: };
+// CHECK-NEXT: return PressureNameTable[Idx];
+// CHECK-NEXT: }
+
+// CHECK: unsigned TestTargetGenRegisterInfo::
+// CHECK-NEXT: getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
+// CHECK-NEXT: static const uint16_t PressureLimitTable[] = {
+// CHECK-NEXT: {{[0-9]+}}, // 0: GPR32
+// CHECK-NEXT: };
+// CHECK-NEXT: return PressureLimitTable[Idx];
+// CHECK-NEXT:}
+
+// CHECK: static const int RCSetsTable[] = {
+// CHECK-NEXT: /* 0 */ 0, -1,
+// CHECK-NEXT: };
+
+def XR32 : RegisterClass<"TestTarget", [i32], 32, (add X0)> {
+ let GeneratePressureSet = 0;
+}
+
+def GPR32_AND_XR32 : RegisterClass<"TestTarget", [i32], 32, (add GPR32, X0)>;
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index 5e88bf8553af..454b05d30297 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -741,6 +741,7 @@ static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) {
CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
: TheDef(R), Name(std::string(R->getName())),
TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1) {
+ GeneratePressureSet = R->getValueAsBit("GeneratePressureSet");
std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
Record *Type = TypeList[i];
@@ -817,6 +818,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1), RSI(Props.RSI),
CopyCost(0), Allocatable(true), AllocationPriority(0) {
Artificial = true;
+ GeneratePressureSet = false;
for (const auto R : Members) {
TopoSigs.set(R->getTopoSig());
Artificial &= R->Artificial;
@@ -839,6 +841,7 @@ void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
Allocatable = Super.Allocatable;
AltOrderSelect = Super.AltOrderSelect;
AllocationPriority = Super.AllocationPriority;
+ GeneratePressureSet |= Super.GeneratePressureSet;
// Copy all allocation orders, filter out foreign registers from the larger
// super-class.
@@ -1892,7 +1895,7 @@ void CodeGenRegBank::computeRegUnitSets() {
// Compute a unique RegUnitSet for each RegClass.
auto &RegClasses = getRegClasses();
for (auto &RC : RegClasses) {
- if (!RC.Allocatable || RC.Artificial)
+ if (!RC.Allocatable || RC.Artificial || !RC.GeneratePressureSet)
continue;
// Speculatively grow the RegUnitSets to hold the new set.
diff --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h
index 510279ddfeb4..f15138b04b01 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/CodeGenRegisters.h
@@ -339,6 +339,9 @@ namespace llvm {
bool CoveredBySubRegs;
/// A register class is artificial if all its members are artificial.
bool Artificial;
+ /// Generate register pressure set for this register class and any class
+ /// synthesized from it.
+ bool GeneratePressureSet;
// Return the Record that defined this class, or NULL if the class was
// created by TableGen.
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