[PATCH] D71492: [SCEV] Generate AddRec for trivial and LCSSA phis outside of loop header (WIP)

Mon Feb 17 10:21:23 PST 2020

fhahn added a comment.

In D71492#1879327 <https://reviews.llvm.org/D71492#1879327>, @Meinersbur wrote:

> What is the status of this? Does it depend on D71538 <https://reviews.llvm.org/D71538>?
>
> If D71538 <https://reviews.llvm.org/D71538> goes in, are this patch and D71539 <https://reviews.llvm.org/D71539> equivalent?

I need to find some time to update the linked patches. But I plan to make some progress over the next week

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71492/new/

https://reviews.llvm.org/D71492