[llvm] 113df90 - [PowerPC] Add the missing InstrAliasing for 64-bit rotate instructions

[QingShan Zhang via llvm-commits]

Author: QingShan Zhang
Date: 2020-02-17T05:42:49Z
New Revision: 113df90388d8b84ea6af0f30b8696a0139ed7088

URL: https://github.com/llvm/llvm-project/commit/113df90388d8b84ea6af0f30b8696a0139ed7088
DIFF: https://github.com/llvm/llvm-project/commit/113df90388d8b84ea6af0f30b8696a0139ed7088.diff

LOG: [PowerPC] Add the missing InstrAliasing for 64-bit rotate instructions

We have the InstAlias rules for 32-bit rotate but missing the 64-bit one.
Rotate left immediate rotlwi ra,rs,n rlwinm ra,rs,n,0,31
Rotate left rotlw ra,rs,rb rlwnm ra,rs,rb,0,31

Differential Revision: https://reviews.llvm.org/D72676

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCInstr64Bit.td
    llvm/test/CodeGen/PowerPC/bperm.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index 43431a1e0069..f870194656e0 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -909,6 +909,10 @@ def ISEL8   : AForm_4<31, 15,
 }  // hasSideEffects = 0
 }  // End FXU Operations.
 
+def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;
+def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;
+def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
+def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
 
 //===----------------------------------------------------------------------===//
 // Load/Store instructions.

diff  --git a/llvm/test/CodeGen/PowerPC/bperm.ll b/llvm/test/CodeGen/PowerPC/bperm.ll
index 2f3118a7f395..53b19620ec13 100644
--- a/llvm/test/CodeGen/PowerPC/bperm.ll
+++ b/llvm/test/CodeGen/PowerPC/bperm.ll
@@ -9,7 +9,7 @@ entry:
   ret i32 %0
 
 ; CHECK-LABEL: @bs4
-; CHECK: rlwinm [[REG1:[0-9]+]], 3, 8, 0, 31
+; CHECK: rotlwi [[REG1:[0-9]+]], 3, 8
 ; CHECK: rlwimi [[REG1]], 3, 24, 16, 23
 ; CHECK: rlwimi [[REG1]], 3, 24, 0, 7
 ; CHECK: mr 3, [[REG1]]