[llvm] dd0b18e - [X86] Disable load folding for X86ISD::ADD with 128 as an immediate.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Sun Feb 16 20:53:23 PST 2020


Author: Craig Topper
Date: 2020-02-16T20:52:51-08:00
New Revision: dd0b18e1eccb8786bcfe0ee7bcf20d988cbc5743

URL: https://github.com/llvm/llvm-project/commit/dd0b18e1eccb8786bcfe0ee7bcf20d988cbc5743
DIFF: https://github.com/llvm/llvm-project/commit/dd0b18e1eccb8786bcfe0ee7bcf20d988cbc5743.diff

LOG: [X86] Disable load folding for X86ISD::ADD with 128 as an immediate.

It can be turned into a sub with -128 instead as long as the
carry flag isn't used.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/test/CodeGen/X86/add.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 24d46da80c08..a3d383b0f55d 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -643,6 +643,11 @@ X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
         if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB) &&
             (-Imm->getAPIntValue()).isSignedIntN(8))
           return false;
+
+        if ((U->getOpcode() == X86ISD::ADD || U->getOpcode() == X86ISD::SUB) &&
+            (-Imm->getAPIntValue()).isSignedIntN(8) &&
+            hasNoCarryFlagUses(SDValue(U, 1)))
+          return false;
       }
 
       // If the other operand is a TLS address, we should fold it instead.

diff  --git a/llvm/test/CodeGen/X86/add.ll b/llvm/test/CodeGen/X86/add.ll
index 1662562bd013..9de564515873 100644
--- a/llvm/test/CodeGen/X86/add.ll
+++ b/llvm/test/CodeGen/X86/add.ll
@@ -560,8 +560,8 @@ declare void @bar_i64(i64)
 define void @add_i32_128_flag(i32 %x) {
 ; X32-LABEL: add_i32_128_flag:
 ; X32:       # %bb.0: # %entry
-; X32-NEXT:    movl $128, %eax
-; X32-NEXT:    addl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    subl $-128, %eax
 ; X32-NEXT:    je .LBB19_2
 ; X32-NEXT:  # %bb.1: # %if.then
 ; X32-NEXT:    pushl %eax


        


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