[llvm] 24c1561 - AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 16 20:06:33 PST 2020
Author: Matt Arsenault
Date: 2020-02-16T22:48:42-05:00
New Revision: 24c156194bfcdae5c5500e2bb8b615f5aaa7e6dc
URL: https://github.com/llvm/llvm-project/commit/24c156194bfcdae5c5500e2bb8b615f5aaa7e6dc
DIFF: https://github.com/llvm/llvm-project/commit/24c156194bfcdae5c5500e2bb8b615f5aaa7e6dc.diff
LOG: AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
index 9c9cad19ec9b..390fbe158cdd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
@@ -161,6 +161,62 @@ body: |
$vgpr0 = COPY %5
...
+---
+name: test_icmp_s24
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; GFX7-LABEL: name: test_icmp_s24
+ ; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
+ ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
+ ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GFX7: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
+ ; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+ ; GFX7: $vgpr0 = COPY [[COPY5]](s32)
+ ; GFX8-LABEL: name: test_icmp_s24
+ ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
+ ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
+ ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
+ ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+ ; GFX8: $vgpr0 = COPY [[COPY5]](s32)
+ ; GFX9-LABEL: name: test_icmp_s24
+ ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
+ ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
+ ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+ ; GFX9: $vgpr0 = COPY [[COPY5]](s32)
+ %0:_(s24) = G_CONSTANT i24 0
+ %1:_(s32) = COPY $vgpr0
+ %2:_(s24) = G_TRUNC %1
+ %3:_(s1) = G_ICMP intpred(ne), %0, %2
+ %4:_(s24) = G_SELECT %3, %0, %2
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
+
---
name: test_icmp_v2s32
body: |
@@ -780,3 +836,45 @@ body: |
%5:_(<2 x s32>) = G_SELECT %4, %2, %3
$vgpr0_vgpr1 = COPY %5
...
+
+---
+name: test_icmp_s33
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; GFX7-LABEL: name: test_icmp_s33
+ ; GFX7: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX7: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; GFX7: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
+ ; GFX7: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; GFX7: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
+ ; GFX7: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; GFX7: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]]
+ ; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[AND1]]
+ ; GFX7: S_ENDPGM 0, implicit [[ICMP]](s1)
+ ; GFX8-LABEL: name: test_icmp_s33
+ ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX8: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; GFX8: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
+ ; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; GFX8: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
+ ; GFX8: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; GFX8: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]]
+ ; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[AND1]]
+ ; GFX8: S_ENDPGM 0, implicit [[ICMP]](s1)
+ ; GFX9-LABEL: name: test_icmp_s33
+ ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[AND1]]
+ ; GFX9: S_ENDPGM 0, implicit [[ICMP]](s1)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s33) = G_TRUNC %0
+ %2:_(s33) = G_CONSTANT i33 0
+ %3:_(s1) = G_ICMP intpred(ne), %2, %2
+ S_ENDPGM 0, implicit %3
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
index 87c72f1154c0..e503d07c994e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
@@ -160,3 +160,40 @@ body: |
%1:_(<2 x p0>) = G_INTTOPTR %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...
+
+---
+name: test_inttoptr_s29_to_p3
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_inttoptr_s29_to_p3
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 536870911
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[AND]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[INTTOPTR]](p3)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s29) = G_TRUNC %0
+ %2:_(p3) = G_INTTOPTR %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: test_inttoptr_s33_to_p3
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_inttoptr_s33_to_p3
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s33) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC]](s33)
+ ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC1]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[INTTOPTR]](p3)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s33) = G_TRUNC %0
+ %2:_(p3) = G_INTTOPTR %1
+ S_ENDPGM 0, implicit %2
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir
index 732d6b71a3c4..058880238b6a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir
@@ -161,3 +161,35 @@ body: |
%1:_(<2 x s32>) = G_PTRTOINT %0
$vgpr0_vgpr1 = COPY %1
...
+
+---
+name: test_ptrtoint_p3_to_s29
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_ptrtoint_p3_to_s29
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s29) = G_TRUNC [[PTRTOINT]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s29)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s29) = G_PTRTOINT %0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: test_ptrtoint_p3_to_s33
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_ptrtoint_p3_to_s33
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s33) = G_ZEXT [[PTRTOINT]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[ZEXT]](s33)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s33) = G_PTRTOINT %0
+ S_ENDPGM 0, implicit %1
+...
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