[PATCH] D74629: AMDGPU/GlobalISel: Improve 16-bit bswap

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll:348
+; GFX7-NEXT:    s_or_b32 s0, s0, s1
+; GFX7-NEXT:    s_bfe_u32 s0, s0, 0x100000
 ; GFX7-NEXT:    ; return to shader part epilog
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Why do we get masking both before and after the operation (s_and and s_bfe)? It seems like only one or the other should be required, depending on whether the upper bits of the register are undefined or defined to be zero.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74629/new/

https://reviews.llvm.org/D74629