[llvm] c3c20c8 - [X86] Fix typo in comment. NFC

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Sat Feb 15 13:00:53 PST 2020


Author: Craig Topper
Date: 2020-02-15T12:48:19-08:00
New Revision: c3c20c83f3d3cc78e901f2cc970b44fd0c2e41b2

URL: https://github.com/llvm/llvm-project/commit/c3c20c83f3d3cc78e901f2cc970b44fd0c2e41b2
DIFF: https://github.com/llvm/llvm-project/commit/c3c20c83f3d3cc78e901f2cc970b44fd0c2e41b2.diff

LOG: [X86] Fix typo in comment. NFC

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86FixupBWInsts.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86FixupBWInsts.cpp b/llvm/lib/Target/X86/X86FixupBWInsts.cpp
index f8c4a2adb851..78de041329e2 100644
--- a/llvm/lib/Target/X86/X86FixupBWInsts.cpp
+++ b/llvm/lib/Target/X86/X86FixupBWInsts.cpp
@@ -350,7 +350,7 @@ MachineInstr *FixupBWInstPass::tryReplaceExtend(unsigned New32BitOpcode,
     return nullptr;
 
   // Don't interfere with formation of CBW instructions which should be a
-  // shorter encoding than even the MOVSX32rr8. It's also immunte to partial
+  // shorter encoding than even the MOVSX32rr8. It's also immune to partial
   // merge issues on Intel CPUs.
   if (MI->getOpcode() == X86::MOVSX16rr8 &&
       MI->getOperand(0).getReg() == X86::AX &&


        


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