[PATCH] D74627: [TableGen] Don't elide bitconverts in PatFrag fragments.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham created this revision.
simon_tatham added reviewers: nhaehnle, hfinkel.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

In the DAG pattern backend, `SimplifyTree` simplifies a pattern by
removing bitconverts between two identical types. But that function is
also run on the fragments list in instances of `PatFrags`, in which
the types haven't been specified yet. So the input and output of the
bitconvert always evaluate to the empty set of types, which makes them
compare equal. So the test always passes, and bitconverts are
unconditionally removed from the PatFrag RHS.

Fixed by spotting the empty type set and using it to inhibit the
optimization.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D74627

Files:
  llvm/test/TableGen/simplify-patfrag.td
  llvm/utils/TableGen/CodeGenDAGPatterns.cpp


Index: llvm/utils/TableGen/CodeGenDAGPatterns.cpp
===================================================================
--- llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ llvm/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -2918,8 +2918,15 @@
 
   // If we have a bitconvert with a resolved type and if the source and
   // destination types are the same, then the bitconvert is useless, remove it.
+  //
+  // We make an exception if the types are completely empty. This can come up
+  // when the pattern being simplified is in the Fragments list of a PatFrags,
+  // so that the operand is just an untyped "node". In that situation we leave
+  // bitconverts unsimplified, and simplify them later once the fragment is
+  // expanded into its true context.
   if (N->getOperator()->getName() == "bitconvert" &&
       N->getExtType(0).isValueTypeByHwMode(false) &&
+      !N->getExtType(0).empty() &&
       N->getExtType(0) == N->getChild(0)->getExtType(0) &&
       N->getName().empty()) {
     N = N->getChildShared(0);
Index: llvm/test/TableGen/simplify-patfrag.td
===================================================================
--- /dev/null
+++ llvm/test/TableGen/simplify-patfrag.td
@@ -0,0 +1,38 @@
+// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+// Minimal Target definition
+def DemoInstrInfo : InstrInfo;
+def Demo : Target {
+  let InstructionSet = DemoInstrInfo;
+}
+
+// Some registers which can hold ints or floats
+foreach i = 0-7 in
+  def "R" # i: Register<"r" # i>;
+def GPR : RegisterClass<"Demo", [i32, f32], 32, (sequence "R%u", 0, 7)>;
+
+// Instruction to convert an int to a float
+def i2f : Instruction {
+  let Size = 2;
+  let OutOperandList = (outs GPR:$dst);
+  let InOperandList = (ins GPR:$src);
+  let AsmString = "i2f $dst, $src";
+}
+
+// Some kind of special type-conversion node supported by this target
+def specialconvert : SDNode<"TEST_TARGET_ISD::SPECIAL_CONVERT", SDTUnaryOp>;
+
+// A PatFrags that matches either bitconvert or the special version
+def anyconvert : PatFrags<(ops node:$src),
+                          [(bitconvert node:$src),
+                           (specialconvert node:$src)]>;
+
+// And a rule that matches that PatFrag and turns it into i2f
+def : Pat<(f32 (anyconvert (i32 GPR:$val))), (i2f GPR:$val)>;
+
+// CHECK: SwitchOpcode{{.*}}ISD::BITCAST
+// CHECK: MorphNodeTo1{{.*}}i2f
+// CHECK: SwitchOpcode{{.*}}TEST_TARGET_ISD::SPECIAL_CONVERT
+// CHECK: MorphNodeTo1{{.*}}i2f


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