[PATCH] D74624: [MIPS GlobalISel] Select 4 byte unaligned load and store

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic created this revision.
Petar.Avramovic added reviewers: atanasyan, petarj.
Herald added subscribers: llvm-commits, jrtc27, hiraditya, arichardson, rovka, sdardis.
Herald added a project: LLVM.
Petar.Avramovic added a parent revision: D74623: [MIPS GlobalISel] RegBankSelect G_MERGE_VALUES and G_UNMERGE_VALUES.
Petar.Avramovic added a child revision: D74625: [MIPS GlobalISel] Legalize non-power-of-2 and unaligned load and store.

Improve legality checks for load and store, 4 byte scalar load and store
are now legal for all subtargets.
During regbank selection 4 byte unaligned loads and stores for MIPS32r5
and older get mapped to gprb.
Select 4 byte unaligned loads and stores for MIPS32r5.
Fix tests that unintentionally had unaligned load or store.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D74624

Files:
  llvm/lib/Target/Mips/MipsInstructionSelector.cpp
  llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
  llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_4_unaligned.ll
  llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir

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