[llvm] bfe3779 - AMDGPU: Use v_perm_b32 to implement bswap
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 13 09:45:45 PST 2020
Author: Matt Arsenault
Date: 2020-02-13T09:45:31-08:00
New Revision: bfe3779459eddaf6ad869a9707c827c2a243def6
URL: https://github.com/llvm/llvm-project/commit/bfe3779459eddaf6ad869a9707c827c2a243def6
DIFF: https://github.com/llvm/llvm-project/commit/bfe3779459eddaf6ad869a9707c827c2a243def6.diff
LOG: AMDGPU: Use v_perm_b32 to implement bswap
Also greatly improve i64 lowering. LegalizeIntegerTypes does the
correct narrowing if i64 isn't legal. Just workaround this for
SelectionDAG by making i64 legal and splitting in the patterns.
Added:
Modified:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/test/CodeGen/AMDGPU/bitreverse.ll
llvm/test/CodeGen/AMDGPU/bswap.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 55003521b8b2..e9679cdf9597 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -361,9 +361,13 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
}
- setOperationAction(ISD::BSWAP, MVT::i32, Legal);
setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
+ // FIXME: This should be narrowed to i32, but that only happens if i64 is
+ // illegal.
+ setOperationAction(ISD::BSWAP, MVT::i64, Legal);
+ setOperationAction(ISD::BSWAP, MVT::i32, Legal);
+
// On SI this is s_memtime and s_memrealtime on VI.
setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
setOperationAction(ISD::TRAP, MVT::Other, Custom);
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 2bb4d5979780..9dd51bf4a27d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -1786,6 +1786,55 @@ def : GCNPat <
(V_ALIGNBIT_B32 $a, $a, (i32 8)))
>;
+// FIXME: This should have been narrowed to i32 during legalization.
+// This pattern should also be skipped for GlobalISel
+def : GCNPat <
+ (i64 (bswap i64:$a)),
+ (REG_SEQUENCE VReg_64,
+ (V_BFI_B32 (S_MOV_B32 (i32 0x00ff00ff)),
+ (V_ALIGNBIT_B32 (i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
+ (i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
+ (i32 24)),
+ (V_ALIGNBIT_B32 (i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
+ (i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
+ (i32 8))),
+ sub0,
+ (V_BFI_B32 (S_MOV_B32 (i32 0x00ff00ff)),
+ (V_ALIGNBIT_B32 (i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
+ (i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
+ (i32 24)),
+ (V_ALIGNBIT_B32 (i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
+ (i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
+ (i32 8))),
+ sub1)
+>;
+
+
+let SubtargetPredicate = isGFX8Plus in {
+// Magic number: 3 | (2 << 8) | (1 << 16) | (0 << 24)
+//
+// My reading of the manual suggests we should be using src0 for the
+// register value, but this is what seems to work.
+def : GCNPat <
+ (i32 (bswap i32:$a)),
+ (V_PERM_B32 (i32 0), VSrc_b32:$a, (S_MOV_B32 (i32 0x00010203)))
+>;
+
+// FIXME: This should have been narrowed to i32 during legalization.
+// This pattern should also be skipped for GlobalISel
+def : GCNPat <
+ (i64 (bswap i64:$a)),
+ (REG_SEQUENCE VReg_64,
+ (V_PERM_B32 (i32 0), (EXTRACT_SUBREG VReg_64:$a, sub1),
+ (S_MOV_B32 (i32 0x00010203))),
+ sub0,
+ (V_PERM_B32 (i32 0), (EXTRACT_SUBREG VReg_64:$a, sub0),
+ (S_MOV_B32 (i32 0x00010203))),
+ sub1)
+>;
+
+}
+
let OtherPredicates = [NoFP16Denormals] in {
def : GCNPat<
(fcanonicalize (f16 (VOP3Mods f16:$src, i32:$src_mods))),
diff --git a/llvm/test/CodeGen/AMDGPU/bitreverse.ll b/llvm/test/CodeGen/AMDGPU/bitreverse.ll
index 40bb9be033f8..0c5c54efd856 100644
--- a/llvm/test/CodeGen/AMDGPU/bitreverse.ll
+++ b/llvm/test/CodeGen/AMDGPU/bitreverse.ll
@@ -235,44 +235,21 @@ define amdgpu_kernel void @v_brev_v2i32(<2 x i32> addrspace(1)* noalias %out, <2
define amdgpu_kernel void @s_brev_i64(i64 addrspace(1)* noalias %out, i64 %val) #0 {
; SI-LABEL: s_brev_i64:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
-; SI-NEXT: s_mov_b32 s3, 0
-; SI-NEXT: s_mov_b32 s10, 0xff0000
-; SI-NEXT: s_mov_b32 s11, 0xff00
-; SI-NEXT: s_mov_b32 s7, s3
+; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; SI-NEXT: s_mov_b32 s4, 0xff00ff
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: v_alignbit_b32 v1, s5, v0, 24
-; SI-NEXT: v_alignbit_b32 v0, s5, v0, 8
-; SI-NEXT: s_lshr_b32 s6, s5, 8
-; SI-NEXT: v_and_b32_e32 v1, s10, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xff000000, v0
-; SI-NEXT: s_lshr_b32 s2, s5, 24
-; SI-NEXT: s_and_b32 s6, s6, s11
-; SI-NEXT: s_or_b64 s[6:7], s[6:7], s[2:3]
-; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: s_lshl_b64 s[8:9], s[4:5], 24
-; SI-NEXT: v_or_b32_e32 v0, s6, v0
-; SI-NEXT: v_mov_b32_e32 v1, s7
-; SI-NEXT: s_lshl_b64 s[6:7], s[4:5], 8
-; SI-NEXT: s_lshl_b32 s2, s4, 8
-; SI-NEXT: s_and_b32 s7, s7, 0xff
-; SI-NEXT: s_mov_b32 s6, s3
-; SI-NEXT: s_and_b32 s9, s9, s11
-; SI-NEXT: s_mov_b32 s8, s3
-; SI-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
-; SI-NEXT: s_lshl_b32 s9, s4, 24
-; SI-NEXT: s_and_b32 s5, s2, s10
-; SI-NEXT: s_mov_b32 s4, s3
-; SI-NEXT: s_or_b64 s[2:3], s[8:9], s[4:5]
-; SI-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
-; SI-NEXT: v_or_b32_e32 v2, s2, v0
-; SI-NEXT: v_or_b32_e32 v3, s3, v1
+; SI-NEXT: v_alignbit_b32 v0, s2, s2, 8
+; SI-NEXT: v_alignbit_b32 v1, s2, s2, 24
+; SI-NEXT: v_alignbit_b32 v2, s3, s3, 8
+; SI-NEXT: v_alignbit_b32 v3, s3, s3, 24
+; SI-NEXT: v_bfi_b32 v4, s4, v1, v0
; SI-NEXT: s_mov_b32 s2, 0xf0f0f0f
-; SI-NEXT: v_and_b32_e32 v1, s2, v3
+; SI-NEXT: v_bfi_b32 v2, s4, v3, v2
+; SI-NEXT: v_and_b32_e32 v1, s2, v4
; SI-NEXT: v_and_b32_e32 v0, s2, v2
; SI-NEXT: s_mov_b32 s2, 0xf0f0f0f0
-; SI-NEXT: v_and_b32_e32 v3, s2, v3
+; SI-NEXT: v_and_b32_e32 v3, s2, v4
; SI-NEXT: v_and_b32_e32 v2, s2, v2
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4
@@ -289,7 +266,6 @@ define amdgpu_kernel void @s_brev_i64(i64 addrspace(1)* noalias %out, i64 %val)
; SI-NEXT: s_mov_b32 s2, 0x55555555
; SI-NEXT: v_or_b32_e32 v2, v2, v0
; SI-NEXT: v_or_b32_e32 v3, v3, v1
-; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: v_and_b32_e32 v1, s2, v3
; SI-NEXT: v_and_b32_e32 v0, s2, v2
; SI-NEXT: s_mov_b32 s2, 0xaaaaaaaa
@@ -301,51 +277,23 @@ define amdgpu_kernel void @s_brev_i64(i64 addrspace(1)* noalias %out, i64 %val)
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; FLAT-LABEL: s_brev_i64:
; FLAT: ; %bb.0:
-; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
-; FLAT-NEXT: s_mov_b32 s3, 0
-; FLAT-NEXT: s_mov_b32 s10, 0xff0000
-; FLAT-NEXT: s_mov_b32 s7, s3
+; FLAT-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
+; FLAT-NEXT: v_mov_b32_e32 v0, 0x10203
+; FLAT-NEXT: s_mov_b32 s4, 0xf0f0f0f
; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; FLAT-NEXT: s_waitcnt lgkmcnt(0)
-; FLAT-NEXT: v_mov_b32_e32 v0, s4
-; FLAT-NEXT: v_alignbit_b32 v1, s5, v0, 24
-; FLAT-NEXT: v_alignbit_b32 v0, s5, v0, 8
-; FLAT-NEXT: s_bfe_u32 s6, s5, 0x80010
-; FLAT-NEXT: v_and_b32_e32 v1, s10, v1
-; FLAT-NEXT: v_and_b32_e32 v0, 0xff000000, v0
-; FLAT-NEXT: s_lshr_b32 s2, s5, 24
-; FLAT-NEXT: s_lshl_b32 s6, s6, 8
-; FLAT-NEXT: s_or_b64 s[6:7], s[6:7], s[2:3]
-; FLAT-NEXT: v_or_b32_e32 v0, v0, v1
-; FLAT-NEXT: s_lshl_b64 s[8:9], s[4:5], 24
-; FLAT-NEXT: v_or_b32_e32 v0, s6, v0
-; FLAT-NEXT: v_mov_b32_e32 v1, s7
-; FLAT-NEXT: s_lshl_b64 s[6:7], s[4:5], 8
-; FLAT-NEXT: s_lshl_b32 s2, s4, 8
-; FLAT-NEXT: s_and_b32 s7, s7, 0xff
-; FLAT-NEXT: s_mov_b32 s6, s3
-; FLAT-NEXT: s_and_b32 s9, s9, 0xff00
-; FLAT-NEXT: s_mov_b32 s8, s3
-; FLAT-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
-; FLAT-NEXT: s_lshl_b32 s9, s4, 24
-; FLAT-NEXT: s_and_b32 s5, s2, s10
-; FLAT-NEXT: s_mov_b32 s4, s3
-; FLAT-NEXT: s_or_b64 s[2:3], s[8:9], s[4:5]
-; FLAT-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
-; FLAT-NEXT: v_or_b32_e32 v2, s2, v0
-; FLAT-NEXT: v_or_b32_e32 v3, s3, v1
-; FLAT-NEXT: s_mov_b32 s2, 0xf0f0f0f
-; FLAT-NEXT: v_and_b32_e32 v1, s2, v3
-; FLAT-NEXT: v_and_b32_e32 v0, s2, v2
+; FLAT-NEXT: v_perm_b32 v2, 0, s2, v0
+; FLAT-NEXT: v_perm_b32 v4, 0, s3, v0
; FLAT-NEXT: s_mov_b32 s2, 0xf0f0f0f0
-; FLAT-NEXT: v_and_b32_e32 v3, s2, v3
-; FLAT-NEXT: v_and_b32_e32 v2, s2, v2
+; FLAT-NEXT: v_and_b32_e32 v1, s4, v2
+; FLAT-NEXT: v_and_b32_e32 v0, s4, v4
+; FLAT-NEXT: v_and_b32_e32 v3, s2, v2
+; FLAT-NEXT: v_and_b32_e32 v2, s2, v4
; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3]
; FLAT-NEXT: s_mov_b32 s2, 0x33333333
@@ -391,7 +339,7 @@ define amdgpu_kernel void @v_brev_i64(i64 addrspace(1)* noalias %out, i64 addrsp
; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr64
-; SI-NEXT: s_mov_b32 s0, 0xff00
+; SI-NEXT: s_mov_b32 s0, 0xff00ff
; SI-NEXT: s_mov_b32 s1, 0xf0f0f0f
; SI-NEXT: s_mov_b32 s2, 0xf0f0f0f0
; SI-NEXT: s_mov_b32 s3, 0x33333333
@@ -399,30 +347,16 @@ define amdgpu_kernel void @v_brev_i64(i64 addrspace(1)* noalias %out, i64 addrsp
; SI-NEXT: s_mov_b32 s8, 0x55555555
; SI-NEXT: s_mov_b32 s9, 0xaaaaaaaa
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshl_b64 v[2:3], v[0:1], 8
-; SI-NEXT: v_alignbit_b32 v4, v1, v0, 24
-; SI-NEXT: v_alignbit_b32 v5, v1, v0, 8
-; SI-NEXT: v_lshrrev_b32_e32 v7, 8, v1
-; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v1
-; SI-NEXT: v_lshl_b64 v[1:2], v[0:1], 24
-; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff0000, v0
-; SI-NEXT: v_and_b32_e32 v4, 0xff0000, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xff000000, v5
-; SI-NEXT: v_and_b32_e32 v7, s0, v7
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_and_b32_e32 v2, s0, v2
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: v_or_b32_e32 v5, v7, v6
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_or_b32_e32 v1, v4, v5
-; SI-NEXT: v_or_b32_e32 v3, v0, v2
-; SI-NEXT: v_and_b32_e32 v0, s1, v1
-; SI-NEXT: v_and_b32_e32 v2, s2, v1
-; SI-NEXT: v_and_b32_e32 v1, s1, v3
-; SI-NEXT: v_and_b32_e32 v3, s2, v3
+; SI-NEXT: v_alignbit_b32 v2, v0, v0, 8
+; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24
+; SI-NEXT: v_alignbit_b32 v3, v1, v1, 8
+; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24
+; SI-NEXT: v_bfi_b32 v2, s0, v0, v2
+; SI-NEXT: v_bfi_b32 v4, s0, v1, v3
+; SI-NEXT: v_and_b32_e32 v1, s1, v2
+; SI-NEXT: v_and_b32_e32 v0, s1, v4
+; SI-NEXT: v_and_b32_e32 v3, s2, v2
+; SI-NEXT: v_and_b32_e32 v2, s2, v4
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4
; SI-NEXT: v_or_b32_e32 v3, v3, v1
@@ -452,9 +386,9 @@ define amdgpu_kernel void @v_brev_i64(i64 addrspace(1)* noalias %out, i64 addrsp
; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; FLAT-NEXT: v_lshlrev_b32_e32 v0, 3, v0
-; FLAT-NEXT: v_mov_b32_e32 v4, 8
-; FLAT-NEXT: s_mov_b32 s2, 0xf0f0f0f
-; FLAT-NEXT: s_mov_b32 s3, 0xf0f0f0f0
+; FLAT-NEXT: s_mov_b32 s2, 0x10203
+; FLAT-NEXT: s_mov_b32 s3, 0xf0f0f0f
+; FLAT-NEXT: s_mov_b32 s6, 0xf0f0f0f0
; FLAT-NEXT: s_waitcnt lgkmcnt(0)
; FLAT-NEXT: v_mov_b32_e32 v1, s1
; FLAT-NEXT: v_add_u32_e32 v0, vcc, s0, v0
@@ -462,33 +396,19 @@ define amdgpu_kernel void @v_brev_i64(i64 addrspace(1)* noalias %out, i64 addrsp
; FLAT-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; FLAT-NEXT: s_mov_b32 s0, 0x33333333
; FLAT-NEXT: s_mov_b32 s1, 0xcccccccc
-; FLAT-NEXT: s_mov_b32 s6, 0x55555555
-; FLAT-NEXT: s_mov_b32 s8, 0xaaaaaaaa
+; FLAT-NEXT: s_mov_b32 s8, 0x55555555
+; FLAT-NEXT: s_mov_b32 s9, 0xaaaaaaaa
; FLAT-NEXT: s_mov_b32 s7, 0xf000
; FLAT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; FLAT-NEXT: v_lshlrev_b64 v[2:3], 24, v[0:1]
-; FLAT-NEXT: v_alignbit_b32 v2, v1, v0, 24
-; FLAT-NEXT: v_alignbit_b32 v6, v1, v0, 8
-; FLAT-NEXT: v_lshlrev_b32_sdwa v7, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-; FLAT-NEXT: v_lshlrev_b64 v[4:5], 8, v[0:1]
-; FLAT-NEXT: v_lshlrev_b32_e32 v4, 24, v0
-; FLAT-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; FLAT-NEXT: v_and_b32_e32 v2, 0xff0000, v2
-; FLAT-NEXT: v_and_b32_e32 v6, 0xff000000, v6
-; FLAT-NEXT: v_and_b32_e32 v0, 0xff0000, v0
-; FLAT-NEXT: v_or_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; FLAT-NEXT: v_or_b32_e32 v2, v6, v2
-; FLAT-NEXT: v_and_b32_e32 v3, 0xff00, v3
-; FLAT-NEXT: v_or_b32_e32 v1, v2, v1
-; FLAT-NEXT: v_or_b32_e32 v0, v4, v0
-; FLAT-NEXT: v_or_b32_sdwa v2, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; FLAT-NEXT: v_or_b32_e32 v3, v0, v2
-; FLAT-NEXT: v_and_b32_e32 v0, s2, v1
-; FLAT-NEXT: v_and_b32_e32 v2, s3, v1
-; FLAT-NEXT: v_and_b32_e32 v1, s2, v3
-; FLAT-NEXT: v_and_b32_e32 v3, s3, v3
+; FLAT-NEXT: v_perm_b32 v2, 0, v0, s2
+; FLAT-NEXT: v_perm_b32 v4, 0, v1, s2
+; FLAT-NEXT: v_and_b32_e32 v1, s3, v2
+; FLAT-NEXT: v_and_b32_e32 v0, s3, v4
+; FLAT-NEXT: v_and_b32_e32 v3, s6, v2
+; FLAT-NEXT: v_and_b32_e32 v2, s6, v4
; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3]
+; FLAT-NEXT: s_mov_b32 s6, -1
; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
; FLAT-NEXT: v_and_b32_e32 v1, s0, v3
@@ -499,13 +419,12 @@ define amdgpu_kernel void @v_brev_i64(i64 addrspace(1)* noalias %out, i64 addrsp
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3]
; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
-; FLAT-NEXT: v_and_b32_e32 v1, s6, v3
-; FLAT-NEXT: v_and_b32_e32 v0, s6, v2
-; FLAT-NEXT: v_and_b32_e32 v3, s8, v3
-; FLAT-NEXT: v_and_b32_e32 v2, s8, v2
+; FLAT-NEXT: v_and_b32_e32 v1, s8, v3
+; FLAT-NEXT: v_and_b32_e32 v0, s8, v2
+; FLAT-NEXT: v_and_b32_e32 v3, s9, v3
+; FLAT-NEXT: v_and_b32_e32 v2, s9, v2
; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
-; FLAT-NEXT: s_mov_b32 s6, -1
; FLAT-NEXT: v_or_b32_e32 v1, v3, v1
; FLAT-NEXT: v_or_b32_e32 v0, v2, v0
; FLAT-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
@@ -523,107 +442,58 @@ define amdgpu_kernel void @s_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
-; SI-NEXT: s_mov_b32 s9, 0
-; SI-NEXT: s_mov_b32 s12, 0xff0000
-; SI-NEXT: s_mov_b32 s13, 0xff000000
-; SI-NEXT: s_mov_b32 s14, 0xff00
+; SI-NEXT: s_mov_b32 s8, 0xff00ff
+; SI-NEXT: s_mov_b32 s9, 0x33333333
+; SI-NEXT: s_mov_b32 s10, 0xcccccccc
+; SI-NEXT: s_mov_b32 s11, 0x55555555
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s2
-; SI-NEXT: v_alignbit_b32 v1, s3, v0, 24
-; SI-NEXT: v_alignbit_b32 v0, s3, v0, 8
-; SI-NEXT: s_lshr_b32 s6, s3, 8
-; SI-NEXT: v_and_b32_e32 v1, s12, v1
-; SI-NEXT: v_and_b32_e32 v0, s13, v0
-; SI-NEXT: s_lshr_b32 s8, s3, 24
-; SI-NEXT: s_and_b32 s6, s6, s14
-; SI-NEXT: s_mov_b32 s7, s9
-; SI-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: s_lshl_b32 s8, s2, 8
-; SI-NEXT: v_or_b32_e32 v0, s6, v0
-; SI-NEXT: v_mov_b32_e32 v1, s7
-; SI-NEXT: s_and_b32 s11, s8, s12
-; SI-NEXT: s_lshl_b32 s7, s2, 24
-; SI-NEXT: s_mov_b32 s6, s9
-; SI-NEXT: s_mov_b32 s10, s9
-; SI-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
-; SI-NEXT: s_lshl_b64 s[10:11], s[2:3], 8
-; SI-NEXT: s_lshl_b64 s[2:3], s[2:3], 24
-; SI-NEXT: s_movk_i32 s15, 0xff
-; SI-NEXT: s_and_b32 s11, s11, s15
-; SI-NEXT: s_mov_b32 s10, s9
-; SI-NEXT: s_and_b32 s3, s3, s14
-; SI-NEXT: s_mov_b32 s2, s9
-; SI-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
-; SI-NEXT: s_or_b64 s[2:3], s[6:7], s[2:3]
-; SI-NEXT: v_mov_b32_e32 v4, s0
-; SI-NEXT: v_alignbit_b32 v5, s1, v4, 24
-; SI-NEXT: v_alignbit_b32 v4, s1, v4, 8
-; SI-NEXT: v_or_b32_e32 v2, s2, v0
-; SI-NEXT: s_lshr_b32 s2, s1, 8
-; SI-NEXT: v_or_b32_e32 v3, s3, v1
-; SI-NEXT: v_and_b32_e32 v5, s12, v5
-; SI-NEXT: v_and_b32_e32 v4, s13, v4
-; SI-NEXT: s_lshr_b32 s8, s1, 24
-; SI-NEXT: s_and_b32 s2, s2, s14
-; SI-NEXT: s_mov_b32 s3, s9
-; SI-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
-; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: s_lshl_b32 s8, s0, 8
-; SI-NEXT: v_or_b32_e32 v4, s2, v4
-; SI-NEXT: v_mov_b32_e32 v5, s3
-; SI-NEXT: s_lshl_b32 s3, s0, 24
-; SI-NEXT: s_mov_b32 s2, s9
-; SI-NEXT: s_and_b32 s11, s8, s12
-; SI-NEXT: s_mov_b32 s16, 0xf0f0f0f
-; SI-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
-; SI-NEXT: s_lshl_b64 s[10:11], s[0:1], 8
-; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], 24
-; SI-NEXT: s_mov_b32 s17, 0xf0f0f0f0
-; SI-NEXT: v_and_b32_e32 v0, s16, v2
-; SI-NEXT: v_and_b32_e32 v1, s16, v3
-; SI-NEXT: v_and_b32_e32 v2, s17, v2
-; SI-NEXT: v_and_b32_e32 v3, s17, v3
-; SI-NEXT: s_and_b32 s11, s11, s15
-; SI-NEXT: s_mov_b32 s10, s9
-; SI-NEXT: s_and_b32 s1, s1, s14
-; SI-NEXT: s_mov_b32 s0, s9
-; SI-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11]
+; SI-NEXT: v_alignbit_b32 v0, s2, s2, 8
+; SI-NEXT: v_alignbit_b32 v1, s2, s2, 24
+; SI-NEXT: v_bfi_b32 v3, s8, v1, v0
+; SI-NEXT: v_alignbit_b32 v2, s3, s3, 8
+; SI-NEXT: v_alignbit_b32 v0, s3, s3, 24
+; SI-NEXT: s_mov_b32 s2, 0xf0f0f0f
+; SI-NEXT: v_bfi_b32 v2, s8, v0, v2
+; SI-NEXT: s_mov_b32 s3, 0xf0f0f0f0
+; SI-NEXT: v_and_b32_e32 v0, s2, v2
+; SI-NEXT: v_and_b32_e32 v1, s2, v3
+; SI-NEXT: v_and_b32_e32 v2, s3, v2
+; SI-NEXT: v_and_b32_e32 v3, s3, v3
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4
-; SI-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
-; SI-NEXT: v_or_b32_e32 v6, s0, v4
-; SI-NEXT: v_or_b32_e32 v7, s1, v5
+; SI-NEXT: v_alignbit_b32 v4, s0, s0, 8
+; SI-NEXT: v_alignbit_b32 v5, s0, s0, 24
+; SI-NEXT: v_bfi_b32 v7, s8, v5, v4
+; SI-NEXT: v_alignbit_b32 v4, s1, s1, 8
+; SI-NEXT: v_alignbit_b32 v5, s1, s1, 24
+; SI-NEXT: v_bfi_b32 v6, s8, v5, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v0
-; SI-NEXT: s_mov_b32 s18, 0x33333333
; SI-NEXT: v_or_b32_e32 v3, v3, v1
-; SI-NEXT: s_mov_b32 s19, 0xcccccccc
-; SI-NEXT: v_and_b32_e32 v0, s18, v2
-; SI-NEXT: v_and_b32_e32 v1, s18, v3
-; SI-NEXT: v_and_b32_e32 v4, s16, v6
-; SI-NEXT: v_and_b32_e32 v5, s16, v7
-; SI-NEXT: v_and_b32_e32 v2, s19, v2
-; SI-NEXT: v_and_b32_e32 v3, s19, v3
-; SI-NEXT: v_and_b32_e32 v6, s17, v6
-; SI-NEXT: v_and_b32_e32 v7, s17, v7
+; SI-NEXT: v_and_b32_e32 v0, s9, v2
+; SI-NEXT: v_and_b32_e32 v1, s9, v3
+; SI-NEXT: v_and_b32_e32 v4, s2, v6
+; SI-NEXT: v_and_b32_e32 v5, s2, v7
+; SI-NEXT: v_and_b32_e32 v2, s10, v2
+; SI-NEXT: v_and_b32_e32 v3, s10, v3
+; SI-NEXT: v_and_b32_e32 v6, s3, v6
+; SI-NEXT: v_and_b32_e32 v7, s3, v7
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 2
; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 4
; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 4
; SI-NEXT: v_or_b32_e32 v2, v2, v0
+; SI-NEXT: v_or_b32_e32 v3, v3, v1
; SI-NEXT: v_or_b32_e32 v6, v6, v4
; SI-NEXT: v_or_b32_e32 v7, v7, v5
-; SI-NEXT: s_mov_b32 s20, 0x55555555
-; SI-NEXT: v_or_b32_e32 v3, v3, v1
-; SI-NEXT: s_mov_b32 s21, 0xaaaaaaaa
-; SI-NEXT: v_and_b32_e32 v0, s20, v2
-; SI-NEXT: v_and_b32_e32 v1, s20, v3
-; SI-NEXT: v_and_b32_e32 v4, s18, v6
-; SI-NEXT: v_and_b32_e32 v5, s18, v7
-; SI-NEXT: v_and_b32_e32 v2, s21, v2
-; SI-NEXT: v_and_b32_e32 v3, s21, v3
-; SI-NEXT: v_and_b32_e32 v6, s19, v6
-; SI-NEXT: v_and_b32_e32 v7, s19, v7
+; SI-NEXT: s_mov_b32 s12, 0xaaaaaaaa
+; SI-NEXT: v_and_b32_e32 v0, s11, v2
+; SI-NEXT: v_and_b32_e32 v1, s11, v3
+; SI-NEXT: v_and_b32_e32 v4, s9, v6
+; SI-NEXT: v_and_b32_e32 v5, s9, v7
+; SI-NEXT: v_and_b32_e32 v2, s12, v2
+; SI-NEXT: v_and_b32_e32 v3, s12, v3
+; SI-NEXT: v_and_b32_e32 v6, s10, v6
+; SI-NEXT: v_and_b32_e32 v7, s10, v7
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 2
@@ -631,10 +501,10 @@ define amdgpu_kernel void @s_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2
; SI-NEXT: v_or_b32_e32 v2, v2, v0
; SI-NEXT: v_or_b32_e32 v0, v6, v4
; SI-NEXT: v_or_b32_e32 v7, v7, v5
-; SI-NEXT: v_and_b32_e32 v5, s20, v7
-; SI-NEXT: v_and_b32_e32 v4, s20, v0
-; SI-NEXT: v_and_b32_e32 v6, s21, v0
-; SI-NEXT: v_and_b32_e32 v7, s21, v7
+; SI-NEXT: v_and_b32_e32 v5, s11, v7
+; SI-NEXT: v_and_b32_e32 v4, s11, v0
+; SI-NEXT: v_and_b32_e32 v6, s12, v0
+; SI-NEXT: v_and_b32_e32 v7, s12, v7
; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 1
; SI-NEXT: v_or_b32_e32 v3, v3, v1
@@ -649,107 +519,50 @@ define amdgpu_kernel void @s_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2
; FLAT: ; %bb.0:
; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; FLAT-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
-; FLAT-NEXT: s_mov_b32 s9, 0
-; FLAT-NEXT: s_mov_b32 s12, 0xff0000
-; FLAT-NEXT: s_mov_b32 s13, 0xff000000
-; FLAT-NEXT: s_mov_b32 s7, s9
+; FLAT-NEXT: v_mov_b32_e32 v4, 0x10203
+; FLAT-NEXT: s_mov_b32 s8, 0xf0f0f0f
+; FLAT-NEXT: s_mov_b32 s9, 0xcccccccc
+; FLAT-NEXT: s_mov_b32 s10, 0x55555555
; FLAT-NEXT: s_waitcnt lgkmcnt(0)
-; FLAT-NEXT: v_mov_b32_e32 v0, s2
-; FLAT-NEXT: v_alignbit_b32 v1, s3, v0, 24
-; FLAT-NEXT: v_alignbit_b32 v0, s3, v0, 8
-; FLAT-NEXT: s_bfe_u32 s6, s3, 0x80010
-; FLAT-NEXT: v_and_b32_e32 v1, s12, v1
-; FLAT-NEXT: v_and_b32_e32 v0, s13, v0
-; FLAT-NEXT: s_lshr_b32 s8, s3, 24
-; FLAT-NEXT: s_lshl_b32 s6, s6, 8
-; FLAT-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; FLAT-NEXT: v_or_b32_e32 v0, v0, v1
-; FLAT-NEXT: s_lshl_b32 s8, s2, 8
-; FLAT-NEXT: v_or_b32_e32 v0, s6, v0
-; FLAT-NEXT: v_mov_b32_e32 v1, s7
-; FLAT-NEXT: s_and_b32 s11, s8, s12
-; FLAT-NEXT: s_lshl_b32 s7, s2, 24
-; FLAT-NEXT: s_mov_b32 s6, s9
-; FLAT-NEXT: s_mov_b32 s10, s9
-; FLAT-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
-; FLAT-NEXT: s_lshl_b64 s[10:11], s[2:3], 8
-; FLAT-NEXT: s_movk_i32 s14, 0xff
-; FLAT-NEXT: s_lshl_b64 s[2:3], s[2:3], 24
-; FLAT-NEXT: s_mov_b32 s15, 0xff00
-; FLAT-NEXT: s_and_b32 s11, s11, s14
-; FLAT-NEXT: s_mov_b32 s10, s9
-; FLAT-NEXT: s_and_b32 s3, s3, s15
-; FLAT-NEXT: s_mov_b32 s2, s9
-; FLAT-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
-; FLAT-NEXT: s_or_b64 s[2:3], s[6:7], s[2:3]
-; FLAT-NEXT: v_mov_b32_e32 v4, s0
-; FLAT-NEXT: v_alignbit_b32 v5, s1, v4, 24
-; FLAT-NEXT: v_alignbit_b32 v4, s1, v4, 8
-; FLAT-NEXT: v_or_b32_e32 v2, s2, v0
-; FLAT-NEXT: s_bfe_u32 s2, s1, 0x80010
-; FLAT-NEXT: v_or_b32_e32 v3, s3, v1
-; FLAT-NEXT: v_and_b32_e32 v5, s12, v5
-; FLAT-NEXT: v_and_b32_e32 v4, s13, v4
-; FLAT-NEXT: s_lshr_b32 s8, s1, 24
-; FLAT-NEXT: s_lshl_b32 s2, s2, 8
-; FLAT-NEXT: s_mov_b32 s3, s9
-; FLAT-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
-; FLAT-NEXT: v_or_b32_e32 v4, v4, v5
-; FLAT-NEXT: s_lshl_b32 s8, s0, 8
-; FLAT-NEXT: v_or_b32_e32 v4, s2, v4
-; FLAT-NEXT: v_mov_b32_e32 v5, s3
-; FLAT-NEXT: s_lshl_b32 s3, s0, 24
-; FLAT-NEXT: s_mov_b32 s2, s9
-; FLAT-NEXT: s_and_b32 s11, s8, s12
-; FLAT-NEXT: s_mov_b32 s16, 0xf0f0f0f
-; FLAT-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
-; FLAT-NEXT: s_lshl_b64 s[10:11], s[0:1], 8
-; FLAT-NEXT: s_lshl_b64 s[0:1], s[0:1], 24
-; FLAT-NEXT: s_mov_b32 s17, 0xf0f0f0f0
-; FLAT-NEXT: v_and_b32_e32 v0, s16, v2
-; FLAT-NEXT: v_and_b32_e32 v1, s16, v3
-; FLAT-NEXT: v_and_b32_e32 v2, s17, v2
-; FLAT-NEXT: v_and_b32_e32 v3, s17, v3
-; FLAT-NEXT: s_and_b32 s11, s11, s14
-; FLAT-NEXT: s_mov_b32 s10, s9
-; FLAT-NEXT: s_and_b32 s1, s1, s15
-; FLAT-NEXT: s_mov_b32 s0, s9
-; FLAT-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11]
+; FLAT-NEXT: v_perm_b32 v3, 0, s2, v4
+; FLAT-NEXT: v_perm_b32 v2, 0, s3, v4
+; FLAT-NEXT: s_mov_b32 s2, 0xf0f0f0f0
+; FLAT-NEXT: v_and_b32_e32 v0, s8, v2
+; FLAT-NEXT: v_and_b32_e32 v1, s8, v3
+; FLAT-NEXT: v_and_b32_e32 v2, s2, v2
+; FLAT-NEXT: v_and_b32_e32 v3, s2, v3
; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3]
-; FLAT-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
-; FLAT-NEXT: v_or_b32_e32 v6, s0, v4
-; FLAT-NEXT: v_or_b32_e32 v7, s1, v5
+; FLAT-NEXT: v_perm_b32 v7, 0, s0, v4
+; FLAT-NEXT: v_perm_b32 v6, 0, s1, v4
; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
-; FLAT-NEXT: s_mov_b32 s18, 0x33333333
+; FLAT-NEXT: s_mov_b32 s3, 0x33333333
; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
-; FLAT-NEXT: s_mov_b32 s19, 0xcccccccc
-; FLAT-NEXT: v_and_b32_e32 v0, s18, v2
-; FLAT-NEXT: v_and_b32_e32 v1, s18, v3
-; FLAT-NEXT: v_and_b32_e32 v4, s16, v6
-; FLAT-NEXT: v_and_b32_e32 v5, s16, v7
-; FLAT-NEXT: v_and_b32_e32 v2, s19, v2
-; FLAT-NEXT: v_and_b32_e32 v3, s19, v3
-; FLAT-NEXT: v_and_b32_e32 v6, s17, v6
-; FLAT-NEXT: v_and_b32_e32 v7, s17, v7
+; FLAT-NEXT: v_and_b32_e32 v0, s3, v2
+; FLAT-NEXT: v_and_b32_e32 v1, s3, v3
+; FLAT-NEXT: v_and_b32_e32 v4, s8, v6
+; FLAT-NEXT: v_and_b32_e32 v5, s8, v7
+; FLAT-NEXT: v_and_b32_e32 v2, s9, v2
+; FLAT-NEXT: v_and_b32_e32 v3, s9, v3
+; FLAT-NEXT: v_and_b32_e32 v6, s2, v6
+; FLAT-NEXT: v_and_b32_e32 v7, s2, v7
; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3]
; FLAT-NEXT: v_lshlrev_b64 v[4:5], 4, v[4:5]
; FLAT-NEXT: v_lshrrev_b64 v[6:7], 4, v[6:7]
; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
+; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
; FLAT-NEXT: v_or_b32_e32 v6, v6, v4
; FLAT-NEXT: v_or_b32_e32 v7, v7, v5
-; FLAT-NEXT: s_mov_b32 s20, 0x55555555
-; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
-; FLAT-NEXT: s_mov_b32 s21, 0xaaaaaaaa
-; FLAT-NEXT: v_and_b32_e32 v0, s20, v2
-; FLAT-NEXT: v_and_b32_e32 v1, s20, v3
-; FLAT-NEXT: v_and_b32_e32 v4, s18, v6
-; FLAT-NEXT: v_and_b32_e32 v5, s18, v7
-; FLAT-NEXT: v_and_b32_e32 v2, s21, v2
-; FLAT-NEXT: v_and_b32_e32 v3, s21, v3
-; FLAT-NEXT: v_and_b32_e32 v6, s19, v6
-; FLAT-NEXT: v_and_b32_e32 v7, s19, v7
+; FLAT-NEXT: s_mov_b32 s11, 0xaaaaaaaa
+; FLAT-NEXT: v_and_b32_e32 v0, s10, v2
+; FLAT-NEXT: v_and_b32_e32 v1, s10, v3
+; FLAT-NEXT: v_and_b32_e32 v4, s3, v6
+; FLAT-NEXT: v_and_b32_e32 v5, s3, v7
+; FLAT-NEXT: v_and_b32_e32 v2, s11, v2
+; FLAT-NEXT: v_and_b32_e32 v3, s11, v3
+; FLAT-NEXT: v_and_b32_e32 v6, s9, v6
+; FLAT-NEXT: v_and_b32_e32 v7, s9, v7
; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
; FLAT-NEXT: v_lshlrev_b64 v[4:5], 2, v[4:5]
@@ -757,10 +570,10 @@ define amdgpu_kernel void @s_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2
; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
; FLAT-NEXT: v_or_b32_e32 v0, v6, v4
; FLAT-NEXT: v_or_b32_e32 v7, v7, v5
-; FLAT-NEXT: v_and_b32_e32 v5, s20, v7
-; FLAT-NEXT: v_and_b32_e32 v4, s20, v0
-; FLAT-NEXT: v_and_b32_e32 v6, s21, v0
-; FLAT-NEXT: v_and_b32_e32 v7, s21, v7
+; FLAT-NEXT: v_and_b32_e32 v5, s10, v7
+; FLAT-NEXT: v_and_b32_e32 v4, s10, v0
+; FLAT-NEXT: v_and_b32_e32 v6, s11, v0
+; FLAT-NEXT: v_and_b32_e32 v7, s11, v7
; FLAT-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
; FLAT-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7]
; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
@@ -787,7 +600,7 @@ define amdgpu_kernel void @v_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2
; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 addr64
-; SI-NEXT: s_mov_b32 s0, 0xff00
+; SI-NEXT: s_mov_b32 s0, 0xff00ff
; SI-NEXT: s_mov_b32 s1, 0xf0f0f0f
; SI-NEXT: s_mov_b32 s2, 0xf0f0f0f0
; SI-NEXT: s_mov_b32 s3, 0x33333333
@@ -796,96 +609,66 @@ define amdgpu_kernel void @v_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2
; SI-NEXT: s_mov_b32 s10, 0xaaaaaaaa
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshl_b64 v[4:5], v[2:3], 8
-; SI-NEXT: v_alignbit_b32 v6, v3, v2, 24
-; SI-NEXT: v_alignbit_b32 v7, v3, v2, 8
-; SI-NEXT: v_lshrrev_b32_e32 v9, 8, v3
-; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v3
-; SI-NEXT: v_lshl_b64 v[3:4], v[2:3], 24
-; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v2
-; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v2
-; SI-NEXT: v_lshl_b64 v[2:3], v[0:1], 8
-; SI-NEXT: v_alignbit_b32 v12, v1, v0, 24
-; SI-NEXT: v_alignbit_b32 v13, v1, v0, 8
-; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v1
-; SI-NEXT: v_lshrrev_b32_e32 v15, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v0
-; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v0
-; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 24
-; SI-NEXT: v_and_b32_e32 v6, 0xff0000, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xff000000, v7
-; SI-NEXT: v_mov_b32_e32 v0, 0xff0000
-; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: v_mov_b32_e32 v7, 0xff00
-; SI-NEXT: v_and_b32_e32 v2, v0, v11
-; SI-NEXT: v_and_b32_e32 v11, v0, v12
-; SI-NEXT: v_and_b32_e32 v9, s0, v9
-; SI-NEXT: v_and_b32_e32 v12, 0xff000000, v13
-; SI-NEXT: v_and_b32_e32 v0, v0, v17
-; SI-NEXT: v_and_b32_e32 v13, v7, v15
-; SI-NEXT: v_and_b32_e32 v1, v7, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_or_b32_e32 v2, v10, v2
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_and_b32_e32 v4, s0, v4
-; SI-NEXT: v_or_b32_e32 v7, v16, v0
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_or_b32_e32 v9, v12, v11
-; SI-NEXT: v_or_b32_e32 v10, v13, v14
-; SI-NEXT: v_or_b32_e32 v0, v4, v5
-; SI-NEXT: v_or_b32_e32 v5, v9, v10
-; SI-NEXT: v_or_b32_e32 v6, v6, v8
-; SI-NEXT: v_or_b32_e32 v7, v7, v1
-; SI-NEXT: v_or_b32_e32 v3, v2, v0
-; SI-NEXT: v_and_b32_e32 v0, s1, v6
-; SI-NEXT: v_and_b32_e32 v2, s2, v6
-; SI-NEXT: v_and_b32_e32 v4, s1, v5
-; SI-NEXT: v_and_b32_e32 v6, s2, v5
-; SI-NEXT: v_and_b32_e32 v5, s1, v7
-; SI-NEXT: v_and_b32_e32 v7, s2, v7
-; SI-NEXT: v_and_b32_e32 v1, s1, v3
-; SI-NEXT: v_and_b32_e32 v3, s2, v3
-; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 4
-; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 4
+; SI-NEXT: v_alignbit_b32 v4, v2, v2, 8
+; SI-NEXT: v_alignbit_b32 v2, v2, v2, 24
+; SI-NEXT: v_alignbit_b32 v5, v3, v3, 8
+; SI-NEXT: v_alignbit_b32 v6, v0, v0, 8
+; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24
+; SI-NEXT: v_alignbit_b32 v7, v1, v1, 8
+; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24
+; SI-NEXT: v_alignbit_b32 v3, v3, v3, 24
+; SI-NEXT: v_bfi_b32 v2, s0, v2, v4
+; SI-NEXT: v_bfi_b32 v4, s0, v3, v5
+; SI-NEXT: v_bfi_b32 v6, s0, v0, v6
+; SI-NEXT: v_bfi_b32 v8, s0, v1, v7
+; SI-NEXT: v_and_b32_e32 v1, s1, v2
+; SI-NEXT: v_and_b32_e32 v0, s1, v4
+; SI-NEXT: v_and_b32_e32 v3, s2, v2
+; SI-NEXT: v_and_b32_e32 v2, s2, v4
+; SI-NEXT: v_and_b32_e32 v5, s1, v6
+; SI-NEXT: v_and_b32_e32 v4, s1, v8
+; SI-NEXT: v_and_b32_e32 v7, s2, v6
+; SI-NEXT: v_and_b32_e32 v6, s2, v8
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4
-; SI-NEXT: v_or_b32_e32 v7, v7, v5
-; SI-NEXT: v_or_b32_e32 v6, v6, v4
+; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 4
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 4
; SI-NEXT: v_or_b32_e32 v3, v3, v1
; SI-NEXT: v_or_b32_e32 v2, v2, v0
-; SI-NEXT: v_and_b32_e32 v5, s3, v7
-; SI-NEXT: v_and_b32_e32 v4, s3, v6
-; SI-NEXT: v_and_b32_e32 v7, s8, v7
-; SI-NEXT: v_and_b32_e32 v6, s8, v6
+; SI-NEXT: v_or_b32_e32 v7, v7, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v4
; SI-NEXT: v_and_b32_e32 v1, s3, v3
; SI-NEXT: v_and_b32_e32 v0, s3, v2
+; SI-NEXT: v_and_b32_e32 v5, s3, v7
+; SI-NEXT: v_and_b32_e32 v4, s3, v6
; SI-NEXT: v_and_b32_e32 v3, s8, v3
; SI-NEXT: v_and_b32_e32 v2, s8, v2
-; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 2
-; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 2
+; SI-NEXT: v_and_b32_e32 v7, s8, v7
+; SI-NEXT: v_and_b32_e32 v6, s8, v6
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 2
-; SI-NEXT: v_or_b32_e32 v7, v7, v5
-; SI-NEXT: v_or_b32_e32 v9, v6, v4
+; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 2
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 2
; SI-NEXT: v_or_b32_e32 v3, v3, v1
; SI-NEXT: v_or_b32_e32 v2, v2, v0
-; SI-NEXT: v_and_b32_e32 v5, s9, v7
-; SI-NEXT: v_and_b32_e32 v4, s9, v9
+; SI-NEXT: v_or_b32_e32 v7, v7, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v4
; SI-NEXT: v_and_b32_e32 v1, s9, v3
; SI-NEXT: v_and_b32_e32 v0, s9, v2
-; SI-NEXT: v_and_b32_e32 v6, s10, v7
-; SI-NEXT: v_lshl_b64 v[7:8], v[4:5], 1
-; SI-NEXT: v_and_b32_e32 v5, s10, v9
+; SI-NEXT: v_and_b32_e32 v5, s9, v7
+; SI-NEXT: v_and_b32_e32 v4, s9, v6
; SI-NEXT: v_and_b32_e32 v3, s10, v3
; SI-NEXT: v_and_b32_e32 v2, s10, v2
+; SI-NEXT: v_and_b32_e32 v7, s10, v7
+; SI-NEXT: v_and_b32_e32 v6, s10, v6
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
-; SI-NEXT: v_lshr_b64 v[4:5], v[5:6], 1
+; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 1
; SI-NEXT: v_or_b32_e32 v3, v3, v1
; SI-NEXT: v_or_b32_e32 v2, v2, v0
-; SI-NEXT: v_or_b32_e32 v1, v5, v8
-; SI-NEXT: v_or_b32_e32 v0, v4, v7
+; SI-NEXT: v_or_b32_e32 v1, v7, v5
+; SI-NEXT: v_or_b32_e32 v0, v6, v4
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
@@ -894,64 +677,33 @@ define amdgpu_kernel void @v_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2
; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; FLAT-NEXT: v_lshlrev_b32_e32 v0, 4, v0
-; FLAT-NEXT: v_mov_b32_e32 v8, 8
-; FLAT-NEXT: v_mov_b32_e32 v10, 0xff0000
-; FLAT-NEXT: s_mov_b32 s2, 0xf0f0f0f
+; FLAT-NEXT: s_mov_b32 s2, 0x10203
+; FLAT-NEXT: s_mov_b32 s3, 0xf0f0f0f
+; FLAT-NEXT: s_mov_b32 s8, 0xf0f0f0f0
; FLAT-NEXT: s_waitcnt lgkmcnt(0)
; FLAT-NEXT: v_mov_b32_e32 v1, s1
; FLAT-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; FLAT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; FLAT-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
-; FLAT-NEXT: s_mov_b32 s0, 0xf0f0f0f0
-; FLAT-NEXT: s_mov_b32 s1, 0x33333333
-; FLAT-NEXT: s_mov_b32 s3, 0xcccccccc
-; FLAT-NEXT: s_mov_b32 s8, 0x55555555
-; FLAT-NEXT: s_mov_b32 s9, 0xaaaaaaaa
+; FLAT-NEXT: s_mov_b32 s0, 0x33333333
+; FLAT-NEXT: s_mov_b32 s1, 0xcccccccc
+; FLAT-NEXT: s_mov_b32 s9, 0x55555555
+; FLAT-NEXT: s_mov_b32 s10, 0xaaaaaaaa
; FLAT-NEXT: s_mov_b32 s7, 0xf000
; FLAT-NEXT: s_mov_b32 s6, -1
; FLAT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; FLAT-NEXT: v_lshlrev_b64 v[4:5], 24, v[2:3]
-; FLAT-NEXT: v_lshlrev_b32_sdwa v12, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-; FLAT-NEXT: v_lshlrev_b32_sdwa v15, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-; FLAT-NEXT: v_lshlrev_b64 v[8:9], 8, v[0:1]
-; FLAT-NEXT: v_lshlrev_b64 v[6:7], 8, v[2:3]
-; FLAT-NEXT: v_alignbit_b32 v4, v3, v2, 24
-; FLAT-NEXT: v_alignbit_b32 v11, v3, v2, 8
-; FLAT-NEXT: v_or_b32_sdwa v3, v12, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; FLAT-NEXT: v_or_b32_sdwa v12, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; FLAT-NEXT: v_alignbit_b32 v13, v1, v0, 24
-; FLAT-NEXT: v_alignbit_b32 v14, v1, v0, 8
-; FLAT-NEXT: v_lshlrev_b32_e32 v8, 24, v0
-; FLAT-NEXT: v_lshlrev_b32_e32 v15, 8, v0
-; FLAT-NEXT: v_lshlrev_b64 v[0:1], 24, v[0:1]
-; FLAT-NEXT: v_lshlrev_b32_e32 v6, 24, v2
-; FLAT-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; FLAT-NEXT: v_and_b32_e32 v0, 0xff0000, v4
-; FLAT-NEXT: v_and_b32_e32 v4, 0xff000000, v11
-; FLAT-NEXT: v_and_b32_e32 v2, v10, v2
-; FLAT-NEXT: v_and_b32_e32 v11, v10, v13
-; FLAT-NEXT: v_or_b32_e32 v0, v4, v0
-; FLAT-NEXT: v_and_b32_e32 v1, 0xff00, v1
-; FLAT-NEXT: v_and_b32_e32 v13, 0xff000000, v14
-; FLAT-NEXT: v_and_b32_e32 v4, 0xff00, v5
-; FLAT-NEXT: v_and_b32_e32 v10, v10, v15
-; FLAT-NEXT: v_or_b32_e32 v5, v13, v11
-; FLAT-NEXT: v_or_b32_e32 v2, v6, v2
-; FLAT-NEXT: v_or_b32_e32 v3, v0, v3
-; FLAT-NEXT: v_or_b32_sdwa v0, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; FLAT-NEXT: v_or_b32_e32 v6, v8, v10
-; FLAT-NEXT: v_or_b32_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; FLAT-NEXT: v_or_b32_e32 v7, v2, v0
-; FLAT-NEXT: v_or_b32_e32 v5, v5, v12
-; FLAT-NEXT: v_or_b32_e32 v8, v6, v1
-; FLAT-NEXT: v_and_b32_e32 v0, s2, v3
-; FLAT-NEXT: v_and_b32_e32 v1, s2, v7
-; FLAT-NEXT: v_and_b32_e32 v2, s0, v3
-; FLAT-NEXT: v_and_b32_e32 v3, s0, v7
-; FLAT-NEXT: v_and_b32_e32 v4, s2, v5
-; FLAT-NEXT: v_and_b32_e32 v6, s0, v5
-; FLAT-NEXT: v_and_b32_e32 v5, s2, v8
-; FLAT-NEXT: v_and_b32_e32 v7, s0, v8
+; FLAT-NEXT: v_perm_b32 v6, 0, v0, s2
+; FLAT-NEXT: v_perm_b32 v4, 0, v3, s2
+; FLAT-NEXT: v_perm_b32 v2, 0, v2, s2
+; FLAT-NEXT: v_perm_b32 v8, 0, v1, s2
+; FLAT-NEXT: v_and_b32_e32 v1, s3, v2
+; FLAT-NEXT: v_and_b32_e32 v0, s3, v4
+; FLAT-NEXT: v_and_b32_e32 v3, s8, v2
+; FLAT-NEXT: v_and_b32_e32 v2, s8, v4
+; FLAT-NEXT: v_and_b32_e32 v5, s3, v6
+; FLAT-NEXT: v_and_b32_e32 v4, s3, v8
+; FLAT-NEXT: v_and_b32_e32 v7, s8, v6
+; FLAT-NEXT: v_and_b32_e32 v6, s8, v8
; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3]
; FLAT-NEXT: v_lshlrev_b64 v[4:5], 4, v[4:5]
@@ -960,14 +712,14 @@ define amdgpu_kernel void @v_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2
; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
; FLAT-NEXT: v_or_b32_e32 v7, v7, v5
; FLAT-NEXT: v_or_b32_e32 v6, v6, v4
-; FLAT-NEXT: v_and_b32_e32 v1, s1, v3
-; FLAT-NEXT: v_and_b32_e32 v0, s1, v2
-; FLAT-NEXT: v_and_b32_e32 v5, s1, v7
-; FLAT-NEXT: v_and_b32_e32 v4, s1, v6
-; FLAT-NEXT: v_and_b32_e32 v3, s3, v3
-; FLAT-NEXT: v_and_b32_e32 v2, s3, v2
-; FLAT-NEXT: v_and_b32_e32 v7, s3, v7
-; FLAT-NEXT: v_and_b32_e32 v6, s3, v6
+; FLAT-NEXT: v_and_b32_e32 v1, s0, v3
+; FLAT-NEXT: v_and_b32_e32 v0, s0, v2
+; FLAT-NEXT: v_and_b32_e32 v5, s0, v7
+; FLAT-NEXT: v_and_b32_e32 v4, s0, v6
+; FLAT-NEXT: v_and_b32_e32 v3, s1, v3
+; FLAT-NEXT: v_and_b32_e32 v2, s1, v2
+; FLAT-NEXT: v_and_b32_e32 v7, s1, v7
+; FLAT-NEXT: v_and_b32_e32 v6, s1, v6
; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3]
; FLAT-NEXT: v_lshlrev_b64 v[4:5], 2, v[4:5]
@@ -976,14 +728,14 @@ define amdgpu_kernel void @v_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2
; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
; FLAT-NEXT: v_or_b32_e32 v7, v7, v5
; FLAT-NEXT: v_or_b32_e32 v6, v6, v4
-; FLAT-NEXT: v_and_b32_e32 v1, s8, v3
-; FLAT-NEXT: v_and_b32_e32 v0, s8, v2
-; FLAT-NEXT: v_and_b32_e32 v5, s8, v7
-; FLAT-NEXT: v_and_b32_e32 v4, s8, v6
-; FLAT-NEXT: v_and_b32_e32 v3, s9, v3
-; FLAT-NEXT: v_and_b32_e32 v2, s9, v2
-; FLAT-NEXT: v_and_b32_e32 v7, s9, v7
-; FLAT-NEXT: v_and_b32_e32 v6, s9, v6
+; FLAT-NEXT: v_and_b32_e32 v1, s9, v3
+; FLAT-NEXT: v_and_b32_e32 v0, s9, v2
+; FLAT-NEXT: v_and_b32_e32 v5, s9, v7
+; FLAT-NEXT: v_and_b32_e32 v4, s9, v6
+; FLAT-NEXT: v_and_b32_e32 v3, s10, v3
+; FLAT-NEXT: v_and_b32_e32 v2, s10, v2
+; FLAT-NEXT: v_and_b32_e32 v7, s10, v7
+; FLAT-NEXT: v_and_b32_e32 v6, s10, v6
; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
; FLAT-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/bswap.ll b/llvm/test/CodeGen/AMDGPU/bswap.ll
index fb641fff5ac3..473dc6050930 100644
--- a/llvm/test/CodeGen/AMDGPU/bswap.ll
+++ b/llvm/test/CodeGen/AMDGPU/bswap.ll
@@ -30,6 +30,7 @@ define amdgpu_kernel void @test_bswap_i32(i32 addrspace(1)* %out, i32 addrspace(
; VI-LABEL: test_bswap_i32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: v_mov_b32_e32 v0, 0x10203
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -37,10 +38,7 @@ define amdgpu_kernel void @test_bswap_i32(i32 addrspace(1)* %out, i32 addrspace(
; VI-NEXT: s_load_dword s4, s[6:7], 0x0
; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_alignbit_b32 v0, s4, s4, 8
-; VI-NEXT: v_alignbit_b32 v1, s4, s4, 24
-; VI-NEXT: s_mov_b32 s4, 0xff00ff
-; VI-NEXT: v_bfi_b32 v0, s4, v1, v0
+; VI-NEXT: v_perm_b32 v0, 0, s4, v0
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm
%val = load i32, i32 addrspace(1)* %in, align 4
@@ -71,7 +69,7 @@ define amdgpu_kernel void @test_bswap_v2i32(<2 x i32> addrspace(1)* %out, <2 x i
; VI-LABEL: test_bswap_v2i32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s8, 0xff00ff
+; VI-NEXT: v_mov_b32_e32 v0, 0x10203
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -79,12 +77,8 @@ define amdgpu_kernel void @test_bswap_v2i32(<2 x i32> addrspace(1)* %out, <2 x i
; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_alignbit_b32 v0, s5, s5, 8
-; VI-NEXT: v_alignbit_b32 v1, s5, s5, 24
-; VI-NEXT: v_alignbit_b32 v2, s4, s4, 8
-; VI-NEXT: v_alignbit_b32 v3, s4, s4, 24
-; VI-NEXT: v_bfi_b32 v1, s8, v1, v0
-; VI-NEXT: v_bfi_b32 v0, s8, v3, v2
+; VI-NEXT: v_perm_b32 v1, 0, s5, v0
+; VI-NEXT: v_perm_b32 v0, 0, s4, v0
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm
%val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8
@@ -121,7 +115,7 @@ define amdgpu_kernel void @test_bswap_v4i32(<4 x i32> addrspace(1)* %out, <4 x i
; VI-LABEL: test_bswap_v4i32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s8, 0xff00ff
+; VI-NEXT: v_mov_b32_e32 v0, 0x10203
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -129,18 +123,10 @@ define amdgpu_kernel void @test_bswap_v4i32(<4 x i32> addrspace(1)* %out, <4 x i
; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_load_dwordx4 s[4:7], s[6:7], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_alignbit_b32 v0, s7, s7, 8
-; VI-NEXT: v_alignbit_b32 v1, s7, s7, 24
-; VI-NEXT: v_bfi_b32 v3, s8, v1, v0
-; VI-NEXT: v_alignbit_b32 v2, s6, s6, 8
-; VI-NEXT: v_alignbit_b32 v4, s6, s6, 24
-; VI-NEXT: v_alignbit_b32 v0, s5, s5, 8
-; VI-NEXT: v_alignbit_b32 v1, s5, s5, 24
-; VI-NEXT: v_bfi_b32 v2, s8, v4, v2
-; VI-NEXT: v_bfi_b32 v1, s8, v1, v0
-; VI-NEXT: v_alignbit_b32 v0, s4, s4, 8
-; VI-NEXT: v_alignbit_b32 v4, s4, s4, 24
-; VI-NEXT: v_bfi_b32 v0, s8, v4, v0
+; VI-NEXT: v_perm_b32 v3, 0, s7, v0
+; VI-NEXT: v_perm_b32 v2, 0, s6, v0
+; VI-NEXT: v_perm_b32 v1, 0, s5, v0
+; VI-NEXT: v_perm_b32 v0, 0, s4, v0
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm
%val = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
@@ -189,41 +175,25 @@ define amdgpu_kernel void @test_bswap_v8i32(<8 x i32> addrspace(1)* %out, <8 x i
;
; VI-LABEL: test_bswap_v8i32:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s12, 0xff00ff
-; VI-NEXT: s_mov_b32 s3, 0xf000
-; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-NEXT: v_mov_b32_e32 v4, 0x10203
+; VI-NEXT: s_mov_b32 s11, 0xf000
+; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s0, s4
-; VI-NEXT: s_mov_b32 s1, s5
-; VI-NEXT: s_load_dwordx8 s[4:11], s[6:7], 0x0
+; VI-NEXT: s_mov_b32 s8, s0
+; VI-NEXT: s_mov_b32 s9, s1
+; VI-NEXT: s_load_dwordx8 s[0:7], s[2:3], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_alignbit_b32 v0, s7, s7, 8
-; VI-NEXT: v_alignbit_b32 v1, s7, s7, 24
-; VI-NEXT: v_bfi_b32 v3, s12, v1, v0
-; VI-NEXT: v_alignbit_b32 v2, s6, s6, 8
-; VI-NEXT: v_alignbit_b32 v4, s6, s6, 24
-; VI-NEXT: v_alignbit_b32 v0, s5, s5, 8
-; VI-NEXT: v_alignbit_b32 v1, s5, s5, 24
-; VI-NEXT: v_bfi_b32 v2, s12, v4, v2
-; VI-NEXT: v_bfi_b32 v1, s12, v1, v0
-; VI-NEXT: v_alignbit_b32 v0, s4, s4, 8
-; VI-NEXT: v_alignbit_b32 v4, s4, s4, 24
-; VI-NEXT: v_bfi_b32 v0, s12, v4, v0
-; VI-NEXT: v_alignbit_b32 v4, s11, s11, 8
-; VI-NEXT: v_alignbit_b32 v5, s11, s11, 24
-; VI-NEXT: v_bfi_b32 v7, s12, v5, v4
-; VI-NEXT: v_alignbit_b32 v4, s10, s10, 8
-; VI-NEXT: v_alignbit_b32 v5, s10, s10, 24
-; VI-NEXT: v_bfi_b32 v6, s12, v5, v4
-; VI-NEXT: v_alignbit_b32 v4, s9, s9, 8
-; VI-NEXT: v_alignbit_b32 v5, s9, s9, 24
-; VI-NEXT: v_bfi_b32 v5, s12, v5, v4
-; VI-NEXT: v_alignbit_b32 v4, s8, s8, 8
-; VI-NEXT: v_alignbit_b32 v8, s8, s8, 24
-; VI-NEXT: v_bfi_b32 v4, s12, v8, v4
-; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
-; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; VI-NEXT: v_perm_b32 v3, 0, s3, v4
+; VI-NEXT: v_perm_b32 v2, 0, s2, v4
+; VI-NEXT: v_perm_b32 v1, 0, s1, v4
+; VI-NEXT: v_perm_b32 v0, 0, s0, v4
+; VI-NEXT: v_perm_b32 v7, 0, s7, v4
+; VI-NEXT: v_perm_b32 v6, 0, s6, v4
+; VI-NEXT: v_perm_b32 v5, 0, s5, v4
+; VI-NEXT: v_perm_b32 v4, 0, s4, v4
+; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
+; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; VI-NEXT: s_endpgm
%val = load <8 x i32>, <8 x i32> addrspace(1)* %in, align 32
%bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone
@@ -234,89 +204,35 @@ define amdgpu_kernel void @test_bswap_v8i32(<8 x i32> addrspace(1)* %out, <8 x i
define amdgpu_kernel void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
; SI-LABEL: test_bswap_i64:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
+; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: s_mov_b32 s19, 0xff0000
-; SI-NEXT: s_mov_b32 s9, 0
-; SI-NEXT: s_mov_b32 s15, 0xff00
-; SI-NEXT: s_mov_b32 s11, s9
-; SI-NEXT: s_mov_b32 s12, s9
-; SI-NEXT: s_mov_b32 s14, s9
-; SI-NEXT: s_mov_b32 s16, s9
-; SI-NEXT: s_mov_b32 s18, s9
-; SI-NEXT: s_mov_b32 s0, s4
-; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_mov_b32 s6, 0xff00ff
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s6
-; SI-NEXT: v_alignbit_b32 v1, s7, v0, 24
-; SI-NEXT: v_alignbit_b32 v0, s7, v0, 8
-; SI-NEXT: s_lshr_b32 s8, s7, 24
-; SI-NEXT: s_lshr_b32 s10, s7, 8
-; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 8
-; SI-NEXT: s_lshl_b64 s[20:21], s[6:7], 24
-; SI-NEXT: s_lshl_b32 s17, s6, 24
-; SI-NEXT: s_lshl_b32 s4, s6, 8
-; SI-NEXT: v_and_b32_e32 v1, s19, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xff000000, v0
-; SI-NEXT: s_and_b32 s10, s10, s15
-; SI-NEXT: s_and_b32 s13, s5, 0xff
-; SI-NEXT: s_and_b32 s15, s21, s15
-; SI-NEXT: s_and_b32 s19, s4, s19
-; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: s_or_b64 s[4:5], s[10:11], s[8:9]
-; SI-NEXT: s_or_b64 s[6:7], s[14:15], s[12:13]
-; SI-NEXT: s_or_b64 s[8:9], s[16:17], s[18:19]
-; SI-NEXT: v_or_b32_e32 v0, s4, v0
-; SI-NEXT: v_mov_b32_e32 v1, s5
-; SI-NEXT: s_or_b64 s[4:5], s[8:9], s[6:7]
-; SI-NEXT: v_or_b32_e32 v0, s4, v0
-; SI-NEXT: v_or_b32_e32 v1, s5, v1
+; SI-NEXT: v_alignbit_b32 v0, s4, s4, 8
+; SI-NEXT: v_alignbit_b32 v1, s4, s4, 24
+; SI-NEXT: v_alignbit_b32 v2, s5, s5, 8
+; SI-NEXT: v_alignbit_b32 v3, s5, s5, 24
+; SI-NEXT: v_bfi_b32 v1, s6, v1, v0
+; SI-NEXT: v_bfi_b32 v0, s6, v3, v2
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: test_bswap_i64:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s12, 0xff0000
+; VI-NEXT: v_mov_b32_e32 v0, 0x10203
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
-; VI-NEXT: s_mov_b32 s1, s5
-; VI-NEXT: s_mov_b32 s5, 0
; VI-NEXT: s_mov_b32 s0, s4
-; VI-NEXT: s_mov_b32 s9, s5
+; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s6
-; VI-NEXT: v_alignbit_b32 v1, s7, v0, 24
-; VI-NEXT: v_alignbit_b32 v0, s7, v0, 8
-; VI-NEXT: s_bfe_u32 s8, s7, 0x80010
-; VI-NEXT: v_and_b32_e32 v1, s12, v1
-; VI-NEXT: v_and_b32_e32 v0, 0xff000000, v0
-; VI-NEXT: s_lshr_b32 s4, s7, 24
-; VI-NEXT: s_lshl_b32 s8, s8, 8
-; VI-NEXT: s_or_b64 s[8:9], s[8:9], s[4:5]
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: s_lshl_b64 s[10:11], s[6:7], 24
-; VI-NEXT: v_or_b32_e32 v0, s8, v0
-; VI-NEXT: v_mov_b32_e32 v1, s9
-; VI-NEXT: s_lshl_b64 s[8:9], s[6:7], 8
-; VI-NEXT: s_lshl_b32 s4, s6, 8
-; VI-NEXT: s_and_b32 s9, s9, 0xff
-; VI-NEXT: s_mov_b32 s8, s5
-; VI-NEXT: s_and_b32 s11, s11, 0xff00
-; VI-NEXT: s_mov_b32 s10, s5
-; VI-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
-; VI-NEXT: s_lshl_b32 s11, s6, 24
-; VI-NEXT: s_and_b32 s7, s4, s12
-; VI-NEXT: s_mov_b32 s6, s5
-; VI-NEXT: s_or_b64 s[4:5], s[10:11], s[6:7]
-; VI-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
-; VI-NEXT: v_or_b32_e32 v0, s4, v0
-; VI-NEXT: v_or_b32_e32 v1, s5, v1
+; VI-NEXT: v_perm_b32 v1, 0, s4, v0
+; VI-NEXT: v_perm_b32 v0, 0, s5, v0
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm
%val = load i64, i64 addrspace(1)* %in, align 8
@@ -328,151 +244,43 @@ define amdgpu_kernel void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace(
define amdgpu_kernel void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) nounwind {
; SI-LABEL: test_bswap_v2i64:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: s_mov_b32 s31, 0xff0000
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_load_dwordx4 s[8:11], s[6:7], 0x0
-; SI-NEXT: s_mov_b32 s7, 0
-; SI-NEXT: s_mov_b32 s22, 0xff000000
-; SI-NEXT: s_mov_b32 s27, 0xff00
-; SI-NEXT: s_movk_i32 s25, 0xff
-; SI-NEXT: s_mov_b32 s13, s7
-; SI-NEXT: s_mov_b32 s14, s7
-; SI-NEXT: s_mov_b32 s16, s7
-; SI-NEXT: s_mov_b32 s18, s7
-; SI-NEXT: s_mov_b32 s20, s7
-; SI-NEXT: s_mov_b32 s23, s7
-; SI-NEXT: s_mov_b32 s24, s7
-; SI-NEXT: s_mov_b32 s26, s7
-; SI-NEXT: s_mov_b32 s28, s7
-; SI-NEXT: s_mov_b32 s30, s7
-; SI-NEXT: s_mov_b32 s0, s4
-; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_mov_b32 s8, 0xff00ff
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s10
-; SI-NEXT: v_alignbit_b32 v1, s11, v0, 24
-; SI-NEXT: v_alignbit_b32 v0, s11, v0, 8
-; SI-NEXT: s_lshr_b32 s6, s11, 24
-; SI-NEXT: s_lshr_b32 s12, s11, 8
-; SI-NEXT: s_lshl_b64 s[4:5], s[10:11], 8
-; SI-NEXT: s_lshl_b64 s[32:33], s[10:11], 24
-; SI-NEXT: s_lshl_b32 s19, s10, 24
-; SI-NEXT: s_lshl_b32 s21, s10, 8
-; SI-NEXT: v_mov_b32_e32 v2, s8
-; SI-NEXT: v_alignbit_b32 v3, s9, v2, 24
-; SI-NEXT: v_alignbit_b32 v2, s9, v2, 8
-; SI-NEXT: s_lshr_b32 s32, s9, 8
-; SI-NEXT: s_lshl_b64 s[10:11], s[8:9], 8
-; SI-NEXT: s_and_b32 s15, s5, s25
-; SI-NEXT: s_lshl_b64 s[4:5], s[8:9], 24
-; SI-NEXT: s_lshl_b32 s29, s8, 24
-; SI-NEXT: s_lshl_b32 s4, s8, 8
-; SI-NEXT: v_and_b32_e32 v1, s31, v1
-; SI-NEXT: v_and_b32_e32 v0, s22, v0
-; SI-NEXT: s_and_b32 s12, s12, s27
-; SI-NEXT: s_and_b32 s17, s33, s27
-; SI-NEXT: s_and_b32 s21, s21, s31
-; SI-NEXT: v_and_b32_e32 v3, s31, v3
-; SI-NEXT: v_and_b32_e32 v2, s22, v2
-; SI-NEXT: s_and_b32 s22, s32, s27
-; SI-NEXT: s_and_b32 s25, s11, s25
-; SI-NEXT: s_and_b32 s27, s5, s27
-; SI-NEXT: s_and_b32 s31, s4, s31
-; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: s_or_b64 s[4:5], s[12:13], s[6:7]
-; SI-NEXT: s_or_b64 s[10:11], s[16:17], s[14:15]
-; SI-NEXT: s_or_b64 s[12:13], s[18:19], s[20:21]
-; SI-NEXT: v_or_b32_e32 v1, v2, v3
-; SI-NEXT: s_lshr_b32 s6, s9, 24
-; SI-NEXT: s_or_b64 s[8:9], s[26:27], s[24:25]
-; SI-NEXT: s_or_b64 s[14:15], s[28:29], s[30:31]
-; SI-NEXT: v_or_b32_e32 v0, s4, v0
-; SI-NEXT: v_mov_b32_e32 v3, s5
-; SI-NEXT: s_or_b64 s[4:5], s[12:13], s[10:11]
-; SI-NEXT: s_or_b64 s[6:7], s[22:23], s[6:7]
-; SI-NEXT: s_or_b64 s[8:9], s[14:15], s[8:9]
-; SI-NEXT: v_or_b32_e32 v2, s4, v0
-; SI-NEXT: v_or_b32_e32 v3, s5, v3
-; SI-NEXT: v_or_b32_e32 v0, s6, v1
-; SI-NEXT: v_mov_b32_e32 v1, s7
-; SI-NEXT: v_or_b32_e32 v0, s8, v0
-; SI-NEXT: v_or_b32_e32 v1, s9, v1
+; SI-NEXT: v_alignbit_b32 v0, s6, s6, 8
+; SI-NEXT: v_alignbit_b32 v1, s6, s6, 24
+; SI-NEXT: v_alignbit_b32 v2, s7, s7, 8
+; SI-NEXT: v_alignbit_b32 v4, s7, s7, 24
+; SI-NEXT: v_alignbit_b32 v5, s4, s4, 8
+; SI-NEXT: v_alignbit_b32 v6, s4, s4, 24
+; SI-NEXT: v_alignbit_b32 v7, s5, s5, 8
+; SI-NEXT: v_alignbit_b32 v8, s5, s5, 24
+; SI-NEXT: v_bfi_b32 v3, s8, v1, v0
+; SI-NEXT: v_bfi_b32 v2, s8, v4, v2
+; SI-NEXT: v_bfi_b32 v1, s8, v6, v5
+; SI-NEXT: v_bfi_b32 v0, s8, v8, v7
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: test_bswap_v2i64:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s9, 0
-; VI-NEXT: s_mov_b32 s14, 0xff0000
-; VI-NEXT: s_mov_b32 s15, 0xff000000
-; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: v_mov_b32_e32 v0, 0x10203
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_load_dwordx4 s[4:7], s[6:7], 0x0
-; VI-NEXT: s_movk_i32 s16, 0xff
-; VI-NEXT: s_mov_b32 s17, 0xff00
-; VI-NEXT: s_mov_b32 s3, 0xf000
-; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s6
-; VI-NEXT: v_alignbit_b32 v1, s7, v0, 24
-; VI-NEXT: v_alignbit_b32 v0, s7, v0, 8
-; VI-NEXT: s_bfe_u32 s10, s7, 0x80010
-; VI-NEXT: v_and_b32_e32 v1, s14, v1
-; VI-NEXT: v_and_b32_e32 v0, s15, v0
-; VI-NEXT: s_lshr_b32 s8, s7, 24
-; VI-NEXT: s_lshl_b32 s10, s10, 8
-; VI-NEXT: s_or_b64 s[10:11], s[10:11], s[8:9]
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 24
-; VI-NEXT: v_or_b32_e32 v0, s10, v0
-; VI-NEXT: v_mov_b32_e32 v1, s11
-; VI-NEXT: s_lshl_b64 s[10:11], s[6:7], 8
-; VI-NEXT: s_and_b32 s11, s11, s16
-; VI-NEXT: s_mov_b32 s10, s9
-; VI-NEXT: s_and_b32 s13, s13, s17
-; VI-NEXT: s_mov_b32 s12, s9
-; VI-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11]
-; VI-NEXT: s_lshl_b32 s13, s6, 24
-; VI-NEXT: s_lshl_b32 s6, s6, 8
-; VI-NEXT: s_and_b32 s7, s6, s14
-; VI-NEXT: s_mov_b32 s6, s9
-; VI-NEXT: s_or_b64 s[6:7], s[12:13], s[6:7]
-; VI-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
-; VI-NEXT: v_or_b32_e32 v2, s6, v0
-; VI-NEXT: v_mov_b32_e32 v0, s4
-; VI-NEXT: v_or_b32_e32 v3, s7, v1
-; VI-NEXT: v_alignbit_b32 v1, s5, v0, 24
-; VI-NEXT: v_alignbit_b32 v0, s5, v0, 8
-; VI-NEXT: s_bfe_u32 s6, s5, 0x80010
-; VI-NEXT: v_and_b32_e32 v1, s14, v1
-; VI-NEXT: v_and_b32_e32 v0, s15, v0
-; VI-NEXT: s_lshr_b32 s8, s5, 24
-; VI-NEXT: s_lshl_b32 s6, s6, 8
-; VI-NEXT: s_mov_b32 s7, s9
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; VI-NEXT: s_lshl_b64 s[10:11], s[4:5], 24
-; VI-NEXT: v_or_b32_e32 v0, s6, v0
-; VI-NEXT: v_mov_b32_e32 v1, s7
-; VI-NEXT: s_lshl_b64 s[6:7], s[4:5], 8
-; VI-NEXT: s_and_b32 s7, s7, s16
-; VI-NEXT: s_mov_b32 s6, s9
-; VI-NEXT: s_and_b32 s11, s11, s17
-; VI-NEXT: s_mov_b32 s10, s9
-; VI-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7]
-; VI-NEXT: s_lshl_b32 s11, s4, 24
-; VI-NEXT: s_lshl_b32 s4, s4, 8
-; VI-NEXT: s_and_b32 s5, s4, s14
-; VI-NEXT: s_mov_b32 s4, s9
-; VI-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
-; VI-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
-; VI-NEXT: v_or_b32_e32 v0, s4, v0
-; VI-NEXT: v_or_b32_e32 v1, s5, v1
+; VI-NEXT: v_perm_b32 v3, 0, s6, v0
+; VI-NEXT: v_perm_b32 v2, 0, s7, v0
+; VI-NEXT: v_perm_b32 v1, 0, s4, v0
+; VI-NEXT: v_perm_b32 v0, 0, s5, v0
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm
%val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
@@ -484,232 +292,62 @@ define amdgpu_kernel void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i
define amdgpu_kernel void @test_bswap_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) nounwind {
; SI-LABEL: test_bswap_v4i64:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: s_mov_b32 s31, 0xff0000
+; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_load_dwordx8 s[4:11], s[14:15], 0x0
-; SI-NEXT: s_mov_b32 s27, 0xff000000
-; SI-NEXT: s_mov_b32 s34, 0xff00
-; SI-NEXT: s_mov_b32 s14, 0
-; SI-NEXT: s_movk_i32 s36, 0xff
-; SI-NEXT: s_mov_b32 s16, s14
-; SI-NEXT: s_mov_b32 s18, s14
-; SI-NEXT: s_mov_b32 s20, s14
-; SI-NEXT: s_mov_b32 s22, s14
-; SI-NEXT: s_mov_b32 s24, s14
-; SI-NEXT: s_mov_b32 s26, s14
-; SI-NEXT: s_mov_b32 s28, s14
-; SI-NEXT: s_mov_b32 s30, s14
-; SI-NEXT: s_mov_b32 s0, s12
-; SI-NEXT: s_mov_b32 s1, s13
+; SI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: s_mov_b32 s10, -1
+; SI-NEXT: s_mov_b32 s12, 0xff00ff
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s6
-; SI-NEXT: v_alignbit_b32 v1, s7, v0, 24
-; SI-NEXT: v_alignbit_b32 v0, s7, v0, 8
-; SI-NEXT: s_lshr_b32 s35, s7, 24
-; SI-NEXT: s_lshr_b32 s37, s7, 8
-; SI-NEXT: v_mov_b32_e32 v2, s4
-; SI-NEXT: v_alignbit_b32 v3, s5, v2, 24
-; SI-NEXT: v_alignbit_b32 v2, s5, v2, 8
-; SI-NEXT: s_lshr_b32 s38, s5, 24
-; SI-NEXT: s_lshr_b32 s39, s5, 8
-; SI-NEXT: s_lshl_b64 s[12:13], s[6:7], 8
-; SI-NEXT: s_lshl_b64 s[32:33], s[6:7], 24
-; SI-NEXT: s_lshl_b32 s7, s6, 8
-; SI-NEXT: s_and_b32 s15, s13, s36
-; SI-NEXT: s_lshl_b64 s[12:13], s[4:5], 8
-; SI-NEXT: s_and_b32 s17, s33, s34
-; SI-NEXT: s_lshl_b64 s[32:33], s[4:5], 24
-; SI-NEXT: s_lshl_b32 s5, s4, 8
-; SI-NEXT: v_mov_b32_e32 v4, s10
-; SI-NEXT: v_alignbit_b32 v5, s11, v4, 24
-; SI-NEXT: v_alignbit_b32 v4, s11, v4, 8
-; SI-NEXT: s_and_b32 s21, s33, s34
-; SI-NEXT: s_lshl_b64 s[32:33], s[10:11], 24
-; SI-NEXT: s_and_b32 s25, s33, s34
-; SI-NEXT: s_lshl_b64 s[32:33], s[8:9], 24
-; SI-NEXT: s_and_b32 s29, s33, s34
-; SI-NEXT: s_lshr_b32 s12, s11, 24
-; SI-NEXT: s_lshr_b32 s40, s11, 8
-; SI-NEXT: v_mov_b32_e32 v6, s8
-; SI-NEXT: v_alignbit_b32 v7, s9, v6, 24
-; SI-NEXT: v_alignbit_b32 v6, s9, v6, 8
-; SI-NEXT: s_and_b32 s19, s7, s31
-; SI-NEXT: s_lshr_b32 s7, s9, 24
-; SI-NEXT: s_and_b32 s23, s5, s31
-; SI-NEXT: s_lshr_b32 s5, s9, 8
-; SI-NEXT: v_and_b32_e32 v0, s27, v0
-; SI-NEXT: v_and_b32_e32 v2, s27, v2
-; SI-NEXT: v_and_b32_e32 v4, s27, v4
-; SI-NEXT: v_and_b32_e32 v6, s27, v6
-; SI-NEXT: s_lshl_b32 s27, s10, 8
-; SI-NEXT: s_and_b32 s27, s27, s31
-; SI-NEXT: s_lshl_b32 s32, s8, 8
-; SI-NEXT: v_and_b32_e32 v1, s31, v1
-; SI-NEXT: v_and_b32_e32 v3, s31, v3
-; SI-NEXT: v_and_b32_e32 v5, s31, v5
-; SI-NEXT: v_and_b32_e32 v7, s31, v7
-; SI-NEXT: s_and_b32 s31, s32, s31
-; SI-NEXT: s_lshl_b64 s[32:33], s[10:11], 8
-; SI-NEXT: s_and_b32 s11, s37, s34
-; SI-NEXT: s_and_b32 s32, s39, s34
-; SI-NEXT: s_and_b32 s37, s40, s34
-; SI-NEXT: s_and_b32 s5, s5, s34
-; SI-NEXT: s_or_b32 s11, s11, s35
-; SI-NEXT: s_lshl_b64 s[34:35], s[8:9], 8
-; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v3
-; SI-NEXT: s_or_b32 s9, s32, s38
-; SI-NEXT: s_or_b64 s[16:17], s[16:17], s[14:15]
-; SI-NEXT: s_lshl_b32 s15, s6, 24
-; SI-NEXT: v_or_b32_e32 v3, v4, v5
-; SI-NEXT: s_or_b32 s12, s37, s12
-; SI-NEXT: v_or_b32_e32 v4, v6, v7
-; SI-NEXT: s_or_b32 s32, s5, s7
-; SI-NEXT: v_or_b32_e32 v2, s11, v0
-; SI-NEXT: v_or_b32_e32 v0, s9, v1
-; SI-NEXT: s_or_b64 s[6:7], s[14:15], s[18:19]
-; SI-NEXT: s_and_b32 s15, s13, s36
-; SI-NEXT: v_or_b32_e32 v6, s12, v3
-; SI-NEXT: s_or_b64 s[6:7], s[6:7], s[16:17]
-; SI-NEXT: s_or_b64 s[12:13], s[20:21], s[14:15]
-; SI-NEXT: s_lshl_b32 s15, s4, 24
-; SI-NEXT: s_or_b64 s[4:5], s[14:15], s[22:23]
-; SI-NEXT: s_and_b32 s15, s33, s36
-; SI-NEXT: s_or_b64 s[4:5], s[4:5], s[12:13]
-; SI-NEXT: s_or_b64 s[12:13], s[24:25], s[14:15]
-; SI-NEXT: s_lshl_b32 s15, s10, 24
-; SI-NEXT: s_or_b64 s[10:11], s[14:15], s[26:27]
-; SI-NEXT: s_and_b32 s15, s35, s36
-; SI-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_or_b64 s[12:13], s[28:29], s[14:15]
-; SI-NEXT: s_lshl_b32 s15, s8, 24
-; SI-NEXT: s_or_b64 s[8:9], s[14:15], s[30:31]
-; SI-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
-; SI-NEXT: v_or_b32_e32 v4, s32, v4
-; SI-NEXT: v_mov_b32_e32 v3, s7
-; SI-NEXT: v_mov_b32_e32 v1, s5
-; SI-NEXT: v_mov_b32_e32 v7, s11
-; SI-NEXT: v_mov_b32_e32 v5, s9
-; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
-; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-NEXT: v_alignbit_b32 v0, s2, s2, 8
+; SI-NEXT: v_alignbit_b32 v1, s2, s2, 24
+; SI-NEXT: v_alignbit_b32 v2, s3, s3, 8
+; SI-NEXT: v_alignbit_b32 v4, s3, s3, 24
+; SI-NEXT: v_alignbit_b32 v5, s0, s0, 8
+; SI-NEXT: v_alignbit_b32 v6, s0, s0, 24
+; SI-NEXT: v_alignbit_b32 v7, s1, s1, 8
+; SI-NEXT: v_alignbit_b32 v8, s1, s1, 24
+; SI-NEXT: v_alignbit_b32 v9, s6, s6, 8
+; SI-NEXT: v_alignbit_b32 v10, s6, s6, 24
+; SI-NEXT: v_alignbit_b32 v11, s7, s7, 8
+; SI-NEXT: v_alignbit_b32 v12, s7, s7, 24
+; SI-NEXT: v_alignbit_b32 v13, s4, s4, 8
+; SI-NEXT: v_alignbit_b32 v14, s4, s4, 24
+; SI-NEXT: v_alignbit_b32 v15, s5, s5, 8
+; SI-NEXT: v_alignbit_b32 v16, s5, s5, 24
+; SI-NEXT: v_bfi_b32 v3, s12, v1, v0
+; SI-NEXT: v_bfi_b32 v2, s12, v4, v2
+; SI-NEXT: v_bfi_b32 v1, s12, v6, v5
+; SI-NEXT: v_bfi_b32 v0, s12, v8, v7
+; SI-NEXT: v_bfi_b32 v7, s12, v10, v9
+; SI-NEXT: v_bfi_b32 v6, s12, v12, v11
+; SI-NEXT: v_bfi_b32 v5, s12, v14, v13
+; SI-NEXT: v_bfi_b32 v4, s12, v16, v15
+; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
+; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: test_bswap_v4i64:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s16, 0xff0000
-; VI-NEXT: s_mov_b32 s17, 0xff000000
-; VI-NEXT: s_movk_i32 s18, 0xff
-; VI-NEXT: s_mov_b32 s19, 0xff00
+; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-NEXT: v_mov_b32_e32 v4, 0x10203
+; VI-NEXT: s_mov_b32 s11, 0xf000
+; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s0, s4
-; VI-NEXT: s_mov_b32 s1, s5
-; VI-NEXT: s_load_dwordx8 s[4:11], s[6:7], 0x0
-; VI-NEXT: s_mov_b32 s3, 0xf000
-; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_mov_b32 s8, s0
+; VI-NEXT: s_mov_b32 s9, s1
+; VI-NEXT: s_load_dwordx8 s[0:7], s[2:3], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s6
-; VI-NEXT: v_alignbit_b32 v1, s7, v0, 24
-; VI-NEXT: v_alignbit_b32 v0, s7, v0, 8
-; VI-NEXT: s_bfe_u32 s13, s7, 0x80010
-; VI-NEXT: v_and_b32_e32 v1, s16, v1
-; VI-NEXT: v_and_b32_e32 v0, s17, v0
-; VI-NEXT: s_lshr_b32 s12, s7, 24
-; VI-NEXT: s_lshl_b32 s13, s13, 8
-; VI-NEXT: s_or_b32 s12, s13, s12
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v2, s12, v0
-; VI-NEXT: v_mov_b32_e32 v0, s4
-; VI-NEXT: v_alignbit_b32 v1, s5, v0, 24
-; VI-NEXT: v_alignbit_b32 v0, s5, v0, 8
-; VI-NEXT: s_bfe_u32 s13, s5, 0x80010
-; VI-NEXT: v_and_b32_e32 v1, s16, v1
-; VI-NEXT: v_and_b32_e32 v0, s17, v0
-; VI-NEXT: s_lshr_b32 s12, s5, 24
-; VI-NEXT: s_lshl_b32 s13, s13, 8
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: s_or_b32 s12, s13, s12
-; VI-NEXT: v_or_b32_e32 v0, s12, v0
-; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 8
-; VI-NEXT: s_lshl_b64 s[14:15], s[6:7], 24
-; VI-NEXT: s_mov_b32 s12, 0
-; VI-NEXT: s_and_b32 s13, s13, s18
-; VI-NEXT: s_and_b32 s15, s15, s19
-; VI-NEXT: s_mov_b32 s14, s12
-; VI-NEXT: s_or_b64 s[14:15], s[14:15], s[12:13]
-; VI-NEXT: s_lshl_b32 s13, s6, 24
-; VI-NEXT: s_lshl_b32 s6, s6, 8
-; VI-NEXT: s_and_b32 s7, s6, s16
-; VI-NEXT: s_mov_b32 s6, s12
-; VI-NEXT: s_or_b64 s[6:7], s[12:13], s[6:7]
-; VI-NEXT: s_or_b64 s[6:7], s[6:7], s[14:15]
-; VI-NEXT: s_lshl_b64 s[14:15], s[4:5], 8
-; VI-NEXT: s_and_b32 s13, s15, s18
-; VI-NEXT: s_lshl_b64 s[14:15], s[4:5], 24
-; VI-NEXT: s_and_b32 s15, s15, s19
-; VI-NEXT: s_mov_b32 s14, s12
-; VI-NEXT: s_or_b64 s[14:15], s[14:15], s[12:13]
-; VI-NEXT: s_lshl_b32 s13, s4, 24
-; VI-NEXT: s_lshl_b32 s4, s4, 8
-; VI-NEXT: s_and_b32 s5, s4, s16
-; VI-NEXT: s_mov_b32 s4, s12
-; VI-NEXT: s_or_b64 s[4:5], s[12:13], s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, s10
-; VI-NEXT: v_alignbit_b32 v3, s11, v1, 24
-; VI-NEXT: s_or_b64 s[4:5], s[4:5], s[14:15]
-; VI-NEXT: v_alignbit_b32 v1, s11, v1, 8
-; VI-NEXT: s_bfe_u32 s6, s11, 0x80010
-; VI-NEXT: v_and_b32_e32 v3, s16, v3
-; VI-NEXT: v_and_b32_e32 v1, s17, v1
-; VI-NEXT: s_lshr_b32 s4, s11, 24
-; VI-NEXT: s_lshl_b32 s6, s6, 8
-; VI-NEXT: s_or_b32 s4, s6, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
-; VI-NEXT: v_or_b32_e32 v6, s4, v1
-; VI-NEXT: v_mov_b32_e32 v1, s8
-; VI-NEXT: v_alignbit_b32 v3, s9, v1, 24
-; VI-NEXT: v_alignbit_b32 v1, s9, v1, 8
-; VI-NEXT: s_bfe_u32 s6, s9, 0x80010
-; VI-NEXT: s_lshl_b64 s[14:15], s[10:11], 8
-; VI-NEXT: v_and_b32_e32 v3, s16, v3
-; VI-NEXT: v_and_b32_e32 v1, s17, v1
-; VI-NEXT: s_lshr_b32 s4, s9, 24
-; VI-NEXT: s_lshl_b32 s6, s6, 8
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
-; VI-NEXT: s_or_b32 s4, s6, s4
-; VI-NEXT: s_and_b32 s13, s15, s18
-; VI-NEXT: s_lshl_b64 s[14:15], s[10:11], 24
-; VI-NEXT: v_or_b32_e32 v4, s4, v1
-; VI-NEXT: s_lshl_b32 s4, s10, 8
-; VI-NEXT: s_and_b32 s15, s15, s19
-; VI-NEXT: s_mov_b32 s14, s12
-; VI-NEXT: s_or_b64 s[14:15], s[14:15], s[12:13]
-; VI-NEXT: s_lshl_b32 s13, s10, 24
-; VI-NEXT: s_and_b32 s11, s4, s16
-; VI-NEXT: s_mov_b32 s10, s12
-; VI-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11]
-; VI-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
-; VI-NEXT: s_lshl_b64 s[14:15], s[8:9], 8
-; VI-NEXT: s_and_b32 s13, s15, s18
-; VI-NEXT: s_lshl_b64 s[14:15], s[8:9], 24
-; VI-NEXT: s_lshl_b32 s4, s8, 8
-; VI-NEXT: s_and_b32 s15, s15, s19
-; VI-NEXT: s_mov_b32 s14, s12
-; VI-NEXT: s_or_b64 s[14:15], s[14:15], s[12:13]
-; VI-NEXT: s_lshl_b32 s13, s8, 24
-; VI-NEXT: s_and_b32 s9, s4, s16
-; VI-NEXT: s_mov_b32 s8, s12
-; VI-NEXT: s_or_b64 s[8:9], s[12:13], s[8:9]
-; VI-NEXT: s_or_b64 s[8:9], s[8:9], s[14:15]
-; VI-NEXT: v_mov_b32_e32 v5, s9
-; VI-NEXT: v_mov_b32_e32 v7, s11
-; VI-NEXT: v_mov_b32_e32 v1, s5
-; VI-NEXT: v_mov_b32_e32 v3, s7
-; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
-; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; VI-NEXT: v_perm_b32 v3, 0, s2, v4
+; VI-NEXT: v_perm_b32 v2, 0, s3, v4
+; VI-NEXT: v_perm_b32 v1, 0, s0, v4
+; VI-NEXT: v_perm_b32 v0, 0, s1, v4
+; VI-NEXT: v_perm_b32 v7, 0, s6, v4
+; VI-NEXT: v_perm_b32 v6, 0, s7, v4
+; VI-NEXT: v_perm_b32 v5, 0, s4, v4
+; VI-NEXT: v_perm_b32 v4, 0, s5, v4
+; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
+; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; VI-NEXT: s_endpgm
%val = load <4 x i64>, <4 x i64> addrspace(1)* %in, align 32
%bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %val) nounwind readnone
@@ -732,10 +370,8 @@ define float @missing_truncate_promote_bswap(i32 %arg) {
; VI-LABEL: missing_truncate_promote_bswap:
; VI: ; %bb.0: ; %bb
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_alignbit_b32 v1, v0, v0, 8
-; VI-NEXT: v_alignbit_b32 v0, v0, v0, 24
-; VI-NEXT: s_mov_b32 s4, 0xff00ff
-; VI-NEXT: v_bfi_b32 v0, s4, v0, v1
+; VI-NEXT: s_mov_b32 s4, 0x10203
+; VI-NEXT: v_perm_b32 v0, 0, v0, s4
; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; VI-NEXT: s_setpc_b64 s[30:31]
bb:
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