[PATCH] D74338: [RFC][TableGen/RISCV] Support combining AssemblerPredicates with ORs

Wed Feb 12 06:41:01 PST 2020

luismarques added a comment.

This seems reasonable. Looking forward to seeing this fleshed out with tests.
I see no problem with not supporting both AND and OR at the same time for now, as that could be added later if the need becomes clear.

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Comment at: llvm/include/llvm/Target/Target.td:664
+  /// e.g. "ModeTumb|FeatureThumb2" is translated to
+  ///      "(Bits & ModeThumb) != 0 || (Bits & FeatureThumb2) != 0".
   string AssemblerCondString = "";
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Nitpick: this could benefit from a deeper edit to better reflect the new semantics, in a clear way. Be sure to clarify that `,` and `|` are currently mutually exclusive.

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Comment at: llvm/utils/TableGen/SubtargetFeatureInfo.cpp:128
+      PrintFatalError(SFI.TheDef->getLoc(),
+                      "Cannot combine operators in AsmPredicate!");
+    bool SplitOr = Conds.find('|') != StringRef::npos;
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Better to put something that indicates that this isn't currently implemented, but could be supported.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D74338/new/

https://reviews.llvm.org/D74338