[llvm] f734ce0 - AMDGPU: Fix crash on v3i15 kernel arguments

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-02-11T18:11:39-05:00
New Revision: f734ce0488d45c8073892abb6805c9fd9d99fd46

URL: https://github.com/llvm/llvm-project/commit/f734ce0488d45c8073892abb6805c9fd9d99fd46
DIFF: https://github.com/llvm/llvm-project/commit/f734ce0488d45c8073892abb6805c9fd9d99fd46.diff

LOG: AMDGPU: Fix crash on v3i15 kernel arguments

This was split into 3 i15 arguments. The i15 piece needs to be rounded
to a simple MVT for the memory type.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index bf21dedef6dd..24e0b9a6d02e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -1019,6 +1019,8 @@ void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
         assert(MemVT.getVectorNumElements() == 3 ||
                MemVT.getVectorNumElements() == 5);
         MemVT = MemVT.getPow2VectorType(State.getContext());
+      } else if (!MemVT.isSimple() && !MemVT.isVector()) {
+        MemVT = MemVT.getRoundIntegerType(State.getContext());
       }
 
       unsigned PartOffset = 0;

diff  --git a/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll b/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
index 6691696924b4..8a33e92557cb 100644
--- a/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
+++ b/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
@@ -130,3 +130,25 @@ define amdgpu_kernel void @array_3xi16(i8 %arg0, [3 x i16] %arg1) {
   store volatile [3 x i16] %arg1, [3 x i16] addrspace(1)* undef
   ret void
 }
+
+; GCN-LABEL: {{^}}v2i15_arg:
+; GCN: s_load_dword [[DWORD:s[0-9]+]]
+; GCN-DAG: s_bfe_u32 [[BFE:s[0-9]+]], [[DWORD]], 0x100010{{$}}
+; GCN-DAG: s_and_b32 [[AND:s[0-9]+]], [[DWORD]], 0x7fff{{$}}
+define amdgpu_kernel void @v2i15_arg(<2 x i15> addrspace(1)* nocapture %out, <2 x i15> %in) {
+entry:
+  store <2 x i15> %in, <2 x i15> addrspace(1)* %out, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}v3i15_arg:
+; GCN: s_load_dword [[DWORD:s[0-9]+]]
+; GCN: s_lshl_b64
+; GCN: s_and_b32
+; GCN: s_and_b32
+; GCN: s_or_b32
+define amdgpu_kernel void @v3i15_arg(<3 x i15> addrspace(1)* nocapture %out, <3 x i15> %in) {
+entry:
+  store <3 x i15> %in, <3 x i15> addrspace(1)* %out, align 4
+  ret void
+}