[PATCH] D74427: [AArch64][GlobalISel] Properly implement widening for TB(N)Z

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added a reviewer: aemerson.
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls, rovka.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.

When we have to widen to a 64-bit register, we have to emit a SUBREG_TO_REG.

Add a general-purpose widening helper (`widenIfNeeded`), which emits the correct SUBREG_TO_REG instruction based off of a desired size and add a testcase.

Also remove some asserts which are technically incorrect in `emitTestBit`.

- p0 doesn't count as a scalar type, so we need to check `!Ty.isVector()` instead
- Whenever we have a s1, the Size/Bit checks are too conservative, so just remove them

Replace these asserts with less conservative ones where applicable.


https://reviews.llvm.org/D74427

Files:
  llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
  llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir

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