[PATCH] D74281: [AVR] Use correct register class for mul instructions

[Ayke via Phabricator via llvm-commits]

aykevl created this revision.
aykevl added reviewers: shepmaster, dylanmckay.
Herald added subscribers: Jim, hiraditya.
Herald added a project: LLVM.

A number of multiplication instructions (`muls`, `mulsu`, `fmul`, `fmuls`, `fmulsu`) had the wrong register class for an operand. This resulted in the wrong register being used for the instruction.

Example:

  target datalayout = "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8"
  target triple = "avr-atmel-none"
  
  define i16 @sliceAppend(i16, i16, i16, i16, i16, i16) addrspace(1) {
    %d = mul i16 %0, %5
    ret i16 %d
  }

The first instruction would be `muls r24, r31` before this patch. The `r31` should have been `r15` if you look at the intermediate forms during instruction selection / register allocation, but the generated instruction uses `r31`. After this patch, an extra `movw` is inserted to get `%5` in range for `muls`.

To make sure this bug is fixed everywhere, I checked all instructions and found that most multiplication instructions suffered from this bug, which I have fixed with this patch. No other instructions appear to be affected.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D74281

Files:
  llvm/lib/Target/AVR/AVRInstrInfo.td


Index: llvm/lib/Target/AVR/AVRInstrInfo.td
===================================================================
--- llvm/lib/Target/AVR/AVRInstrInfo.td
+++ llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -555,7 +555,7 @@
 
     def MULSRdRr : FMUL2RdRr<0,
                              (outs),
-                             (ins GPR8:$lhs, GPR8:$rhs),
+                             (ins LD8:$lhs, LD8:$rhs),
                              "muls\t$lhs, $rhs",
                              []>,
                    Requires<[SupportsMultiplication]>;
@@ -563,28 +563,28 @@
 
   def MULSURdRr : FMUL2RdRr<1,
                             (outs),
-                            (ins GPR8:$lhs, GPR8:$rhs),
+                            (ins LD8lo:$lhs, LD8lo:$rhs),
                             "mulsu\t$lhs, $rhs",
                             []>,
                   Requires<[SupportsMultiplication]>;
 
   def FMUL : FFMULRdRr<0b01,
                        (outs),
-                       (ins GPR8:$lhs, GPR8:$rhs),
+                       (ins LD8lo:$lhs, LD8lo:$rhs),
                        "fmul\t$lhs, $rhs",
                        []>,
              Requires<[SupportsMultiplication]>;
 
   def FMULS : FFMULRdRr<0b10,
                         (outs),
-                        (ins GPR8:$lhs, GPR8:$rhs),
+                        (ins LD8lo:$lhs, LD8lo:$rhs),
                         "fmuls\t$lhs, $rhs",
                         []>,
               Requires<[SupportsMultiplication]>;
 
   def FMULSU : FFMULRdRr<0b11,
                          (outs),
-                         (ins GPR8:$lhs, GPR8:$rhs),
+                         (ins LD8lo:$lhs, LD8lo:$rhs),
                          "fmulsu\t$lhs, $rhs",
                          []>,
                Requires<[SupportsMultiplication]>;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D74281.243376.patch
Type: text/x-patch
Size: 1790 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200208/3c58ad6e/attachment.bin>