[llvm] 56d81d4 - [Target][AArch64] Remove non-existing system registers ICH_VSEIR_EL2 & ICC_SEIEN_EL1 from AArch64 backend
via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 7 01:49:36 PST 2020
Author: Pierre van Houtryve
Date: 2020-02-07T09:44:41Z
New Revision: 56d81d4580940377a0e3963c4920e70d62eb5620
URL: https://github.com/llvm/llvm-project/commit/56d81d4580940377a0e3963c4920e70d62eb5620
DIFF: https://github.com/llvm/llvm-project/commit/56d81d4580940377a0e3963c4920e70d62eb5620.diff
LOG: [Target][AArch64] Remove non-existing system registers ICH_VSEIR_EL2 & ICC_SEIEN_EL1 from AArch64 backend
Differential Revision: https://reviews.llvm.org/D74118
Added:
Modified:
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/test/MC/AArch64/gicv3-regs.s
llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 6e82d326e519..c7dbd01913ce 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1167,7 +1167,6 @@ def : RWSysReg<"ICC_SRE_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b101>;
def : RWSysReg<"ICC_IGRPEN0_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b110>;
def : RWSysReg<"ICC_IGRPEN1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b111>;
def : RWSysReg<"ICC_IGRPEN1_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b111>;
-def : RWSysReg<"ICC_SEIEN_EL1", 0b11, 0b000, 0b1100, 0b1101, 0b000>;
def : RWSysReg<"ICC_AP0R0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b100>;
def : RWSysReg<"ICC_AP0R1_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b101>;
def : RWSysReg<"ICC_AP0R2_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b110>;
@@ -1187,7 +1186,6 @@ def : RWSysReg<"ICH_AP1R3_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b011>;
def : RWSysReg<"ICH_HCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b000>;
def : RWSysReg<"ICH_MISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b010>;
def : RWSysReg<"ICH_VMCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b111>;
-def : RWSysReg<"ICH_VSEIR_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b100>;
def : RWSysReg<"ICH_LR0_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b000>;
def : RWSysReg<"ICH_LR1_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b001>;
def : RWSysReg<"ICH_LR2_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b010>;
diff --git a/llvm/test/MC/AArch64/gicv3-regs.s b/llvm/test/MC/AArch64/gicv3-regs.s
index ed3599fc956b..faa4a0275b53 100644
--- a/llvm/test/MC/AArch64/gicv3-regs.s
+++ b/llvm/test/MC/AArch64/gicv3-regs.s
@@ -19,7 +19,6 @@
mrs x22, icc_igrpen0_el1
mrs x5, icc_igrpen1_el1
mrs x7, icc_igrpen1_el3
- mrs x22, icc_seien_el1
mrs x4, icc_ap0r0_el1
mrs x11, icc_ap0r1_el1
mrs x27, icc_ap0r2_el1
@@ -39,7 +38,6 @@
mrs x10, ich_hcr_el2
mrs x27, ich_misr_el2
mrs x6, ich_vmcr_el2
- mrs x19, ich_vseir_el2
mrs x3, ich_lr0_el2
mrs x1, ich_lr1_el2
mrs x22, ich_lr2_el2
@@ -75,7 +73,6 @@
// CHECK: mrs x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}} // encoding: [0xd6,0xcc,0x38,0xd5]
// CHECK: mrs x5, {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}} // encoding: [0xe5,0xcc,0x38,0xd5]
// CHECK: mrs x7, {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}} // encoding: [0xe7,0xcc,0x3e,0xd5]
-// CHECK: mrs x22, {{icc_seien_el1|ICC_SEIEN_EL1}} // encoding: [0x16,0xcd,0x38,0xd5]
// CHECK: mrs x4, {{icc_ap0r0_el1|ICC_AP0R0_EL1}} // encoding: [0x84,0xc8,0x38,0xd5]
// CHECK: mrs x11, {{icc_ap0r1_el1|ICC_AP0R1_EL1}} // encoding: [0xab,0xc8,0x38,0xd5]
// CHECK: mrs x27, {{icc_ap0r2_el1|ICC_AP0R2_EL1}} // encoding: [0xdb,0xc8,0x38,0xd5]
@@ -95,7 +92,6 @@
// CHECK: mrs x10, {{ich_hcr_el2|ICH_HCR_EL2}} // encoding: [0x0a,0xcb,0x3c,0xd5]
// CHECK: mrs x27, {{ich_misr_el2|ICH_MISR_EL2}} // encoding: [0x5b,0xcb,0x3c,0xd5]
// CHECK: mrs x6, {{ich_vmcr_el2|ICH_VMCR_EL2}} // encoding: [0xe6,0xcb,0x3c,0xd5]
-// CHECK: mrs x19, {{ich_vseir_el2|ICH_VSEIR_EL2}} // encoding: [0x93,0xc9,0x3c,0xd5]
// CHECK: mrs x3, {{ich_lr0_el2|ICH_LR0_EL2}} // encoding: [0x03,0xcc,0x3c,0xd5]
// CHECK: mrs x1, {{ich_lr1_el2|ICH_LR1_EL2}} // encoding: [0x21,0xcc,0x3c,0xd5]
// CHECK: mrs x22, {{ich_lr2_el2|ICH_LR2_EL2}} // encoding: [0x56,0xcc,0x3c,0xd5]
@@ -130,7 +126,6 @@
msr icc_igrpen0_el1, x22
msr icc_igrpen1_el1, x11
msr icc_igrpen1_el3, x8
- msr icc_seien_el1, x4
msr icc_ap0r0_el1, x27
msr icc_ap0r1_el1, x5
msr icc_ap0r2_el1, x20
@@ -150,7 +145,6 @@
msr ich_hcr_el2, x1
msr ich_misr_el2, x10
msr ich_vmcr_el2, x24
- msr ich_vseir_el2, x29
msr ich_lr0_el2, x26
msr ich_lr1_el2, x9
msr ich_lr2_el2, x18
@@ -184,7 +178,6 @@
// CHECK: msr {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22 // encoding: [0xd6,0xcc,0x18,0xd5]
// CHECK: msr {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x11 // encoding: [0xeb,0xcc,0x18,0xd5]
// CHECK: msr {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x8 // encoding: [0xe8,0xcc,0x1e,0xd5]
-// CHECK: msr {{icc_seien_el1|ICC_SEIEN_EL1}}, x4 // encoding: [0x04,0xcd,0x18,0xd5]
// CHECK: msr {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x27 // encoding: [0x9b,0xc8,0x18,0xd5]
// CHECK: msr {{icc_ap0r1_el1|ICC_AP0R1_EL1}}, x5 // encoding: [0xa5,0xc8,0x18,0xd5]
// CHECK: msr {{icc_ap0r2_el1|ICC_AP0R2_EL1}}, x20 // encoding: [0xd4,0xc8,0x18,0xd5]
@@ -204,7 +197,6 @@
// CHECK: msr {{ich_hcr_el2|ICH_HCR_EL2}}, x1 // encoding: [0x01,0xcb,0x1c,0xd5]
// CHECK: msr {{ich_misr_el2|ICH_MISR_EL2}}, x10 // encoding: [0x4a,0xcb,0x1c,0xd5]
// CHECK: msr {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24 // encoding: [0xf8,0xcb,0x1c,0xd5]
-// CHECK: msr {{ich_vseir_el2|ICH_VSEIR_EL2}}, x29 // encoding: [0x9d,0xc9,0x1c,0xd5]
// CHECK: msr {{ich_lr0_el2|ICH_LR0_EL2}}, x26 // encoding: [0x1a,0xcc,0x1c,0xd5]
// CHECK: msr {{ich_lr1_el2|ICH_LR1_EL2}}, x9 // encoding: [0x29,0xcc,0x1c,0xd5]
// CHECK: msr {{ich_lr2_el2|ICH_LR2_EL2}}, x18 // encoding: [0x52,0xcc,0x1c,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt b/llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt
index aec30c662f72..5c97765eefcf 100644
--- a/llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt
+++ b/llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt
@@ -39,8 +39,6 @@
# CHECK: mrs x5, {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}
0xe7 0xcc 0x3e 0xd5
# CHECK: mrs x7, {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}
-0x16 0xcd 0x38 0xd5
-# CHECK: mrs x22, {{icc_seien_el1|ICC_SEIEN_EL1}}
0x84 0xc8 0x38 0xd5
# CHECK: mrs x4, {{icc_ap0r0_el1|ICC_AP0R0_EL1}}
0xab 0xc8 0x38 0xd5
@@ -79,8 +77,6 @@
# CHECK: mrs x27, {{ich_misr_el2|ICH_MISR_EL2}}
0xe6 0xcb 0x3c 0xd5
# CHECK: mrs x6, {{ich_vmcr_el2|ICH_VMCR_EL2}}
-0x93 0xc9 0x3c 0xd5
-# CHECK: mrs x19, {{ich_vseir_el2|ICH_VSEIR_EL2}}
0x3 0xcc 0x3c 0xd5
# CHECK: mrs x3, {{ich_lr0_el2|ICH_LR0_EL2}}
0x21 0xcc 0x3c 0xd5
@@ -147,8 +143,6 @@
# CHECK: msr {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x11
0xe8 0xcc 0x1e 0xd5
# CHECK: msr {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x8
-0x4 0xcd 0x18 0xd5
-# CHECK: msr {{icc_seien_el1|ICC_SEIEN_EL1}}, x4
0x9b 0xc8 0x18 0xd5
# CHECK: msr {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x27
0xa5 0xc8 0x18 0xd5
@@ -187,8 +181,6 @@
# CHECK: msr {{ich_misr_el2|ICH_MISR_EL2}}, x10
0xf8 0xcb 0x1c 0xd5
# CHECK: msr {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24
-0x9d 0xc9 0x1c 0xd5
-# CHECK: msr {{ich_vseir_el2|ICH_VSEIR_EL2}}, x29
0x1a 0xcc 0x1c 0xd5
# CHECK: msr {{ich_lr0_el2|ICH_LR0_EL2}}, x26
0x29 0xcc 0x1c 0xd5
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