[PATCH] D57504: RFC: Prototype & Roadmap for vector predication in LLVM

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

> 2.) Optimization passes and (vectorizing) frontends
>  Vectorizers/frontends should query TTI to decide whether they should be using `%evl`.
>  For VL targets, the loop vectorizer could use `%evl` to implement tail loop predication (as in the DAXPY example https://www.sigarch.org/simd-instructions-considered-harmful/ , linked by @lkcl).
>  For non-VL targets, you should make the iteration mask the root mask of all other predicates in the loop and set `%evl` to `-1`.

FWIW this is the approach we plan to use at BSC to vectorize using RISC-V extension. We're currently adding mask information to VPlan recipes that when executed should emit VPred operations with masking. Our plan includes a vplan→vplan transformation that would express the "root" mask as a "set vector length" operation.


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