[PATCH] D73602: [SVE] Add support for lowering GEPs involving scalable vectors.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli added a subscriber: eli.friedman.
fpetrogalli added a comment.

Hi @eli.friedman ,

thank you for working on this, I am working on adding the addressing modes for SVE, this is required to be able to test what I am doing in the back-end.

I have the following questions/requests.

1. Could you please describe in a comment in the tests the math behind operations like the following? `%d = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, <2 x i64> <i64 1, i64 1>`. This could be determined by looking at the codegen, but having it explained in a target independent representation would make things easier to undertsand.
2. Could you please tests expressions like the following? `getelementptr <vscale x 2 x i64>,  <vscale x 2 x i64> * %base, i64 4`,   ` getelementptr <vscale x 2 x i64>,  <vscale x 2 x i64> * %base, [i32|i64] %offset` and `getelementptr i8, <vscale x 2 x i8*> %bases, i32 1`?
3. You tests the cases for `<vscale x 2 x i64>`. Could you please test more configurations of `<vscale x N x Ty>`, at least covering all cases in which `sizeof( N x Ty) == 16`?

All these requests will probably require you to add more patterns in `AArch64SVEInstrInfo.td`, other than the one you have already added. If that's the case, I think it will be worth splitting the patch in two patches, one for the CodeGen of the patterns and one for the codegen of the GEP (of course, unless it is not possible to reproduce such patterns without the GEP on scalable types...)

Thanks!

Francesco


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73602/new/

https://reviews.llvm.org/D73602