[llvm] cd14b4a - [X86] Remove unneeded code that looks for (and (i8 (X86setcc_c))

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-02-03T23:18:11-08:00
New Revision: cd14b4a62bdb78ba31d30871c1dfb27517721862

URL: https://github.com/llvm/llvm-project/commit/cd14b4a62bdb78ba31d30871c1dfb27517721862
DIFF: https://github.com/llvm/llvm-project/commit/cd14b4a62bdb78ba31d30871c1dfb27517721862.diff

LOG: [X86] Remove unneeded code that looks for (and (i8 (X86setcc_c))

I don't believe we use this construct anymore so I don't think
we need to look for it.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/lib/Target/X86/X86InstrCompiler.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 0eee4e0d0913..b828b77d07a2 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -43869,28 +43869,10 @@ static SDValue combineFMADDSUB(SDNode *N, SelectionDAG &DAG,
 static SDValue combineZext(SDNode *N, SelectionDAG &DAG,
                            TargetLowering::DAGCombinerInfo &DCI,
                            const X86Subtarget &Subtarget) {
-  // (i32 zext (and (i8  x86isd::setcc_carry), 1)) ->
-  //           (and (i32 x86isd::setcc_carry), 1)
-  // This eliminates the zext. This transformation is necessary because
-  // ISD::SETCC is always legalized to i8.
   SDLoc dl(N);
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
 
-  if (N0.getOpcode() == ISD::AND &&
-      N0.hasOneUse() &&
-      N0.getOperand(0).hasOneUse()) {
-    SDValue N00 = N0.getOperand(0);
-    if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
-      if (!isOneConstant(N0.getOperand(1)))
-        return SDValue();
-      return DAG.getNode(ISD::AND, dl, VT,
-                         DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
-                                     N00.getOperand(0), N00.getOperand(1)),
-                         DAG.getConstant(1, dl, VT));
-    }
-  }
-
   if (SDValue NewCMov = combineToExtendCMOV(N, DAG))
     return NewCMov;
 

diff  --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index 78d8dd3c0d03..841453ef1074 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -349,13 +349,6 @@ def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
           (SETB_C64r)>;
 
-// We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
-// will be eliminated and that the sbb can be extended up to a wider type.  When
-// this happens, it is great.  However, if we are left with an 8-bit sbb and an
-// and, we might as well just match it as a setb.
-def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
-          (SETCCr (i8 2))>;
-
 // Patterns to give priority when both inputs are zero so that we don't use
 // an immediate for the RHS.
 // TODO: Should we use a 32-bit sbb for 8/16 to push the extract_subreg out?