[PATCH] D73882: CodeGen: Add TIED_COPY instruction

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: qcolombet, nhaehnle.
Herald added subscribers: kerbowa, hiraditya, wdng, jvesely.
Herald added a project: LLVM.

I need a way to be able to constrain a register def to use the same
input register throughout a loop. For a VGPR, we don't model the other
live values in other lanes. In cases where we are explicitly
scalarizing operations and writing different lanes sequentially, we
need to model this as an input tied operand to the def instruction
inside the loop. The verifier doesn't allow adding a tied implicit use
to an explicit def, so move this constraint into a copy we can use to
accumulate the real result. This should be folded out after allocation
like a normal copy when possible.


https://reviews.llvm.org/D73882

Files:
  llvm/include/llvm/CodeGen/MachineInstr.h
  llvm/include/llvm/Support/TargetOpcodes.def
  llvm/include/llvm/Target/Target.td
  llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
  llvm/lib/CodeGen/VirtRegMap.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp

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