[PATCH] D73749: [LegalizeTypes][X86] Add a new strategy for type legalizing f16 type that softens it to i16, but promotes to f32 around arithmetic ops.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:2685
+  // Convert back to FP16 as an integer.
+  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
+  return DAG.getNode(ISD::FP_TO_FP16, dl, IVT, Res);
----------------
efriedma wrote:
> Using getIntegerVT like this is suspicious; if the original node is a vector, the promoted node should also be a vector, no?
Wait, nevermind; the original node can't be a vector.  We would split/scalarize the vector first.

In that case, you might as well just write MVT::i16 explicitly, though.


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:2766
+
+SDValue DAGTypeLegalizer::SoftPromoteHalfOp_INSERT_VECTOR_ELT(SDNode *N,
+                                                              unsigned OpNo) {
----------------
Is SoftPromoteHalfOp_INSERT_VECTOR_ELT actually reachable?  If the operand is a half-float, the result would have to be a half vector, and we would split that, I think?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73749/new/

https://reviews.llvm.org/D73749