[PATCH] D73483: [AMDGPU] fixed divergence driven shift operations selection

Alexander via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 29 05:22:40 PST 2020


alex-t added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/VOP2Instructions.td:548
 } // End SubtargetPredicate = isGFX6GFX7GFX10
+let SubtargetPredicate = isGFX6GFX7 in {
+defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, srl>;
----------------
rampitec wrote:
> Any tests for GFX10 on this?
Will be an assertion "Opcode does not exist on target"


================
Comment at: llvm/lib/Target/AMDGPU/VOP3Instructions.td:388
 let SchedRW = [Write64Bit] in {
-let SubtargetPredicate = isGFX6GFX7GFX10 in {
+let SubtargetPredicate = isGFX6GFX7 in {
 def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, shl>;
----------------
rampitec wrote:
> Any tests for GFX10 on this?
Will be an assertion "Opcode does not exist on target"


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73483/new/

https://reviews.llvm.org/D73483





More information about the llvm-commits mailing list