[PATCH] D73480: [VectorCombine] new IR transform pass for partial vector ops

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D73480#1844833 <https://reviews.llvm.org/D73480#1844833>, @RKSimon wrote:

> Thanks for working on this @spatel - I'm interested to see how far we can take cost driven combines (without conflicting with canonicalizations in other passes).
>
> You mention that you want this to begin as a relatively safe set of combines, but it's probably necessary to get some idea of where you see this going and the range of optimizations it could handle (for instance - are memory ops being considered......)?


Yes, I think we could handle some load/store patterns. Note that there is already a LoadStoreVectorizer pass for IR, but it's currently only used for GPU targets as a pre-codegen cleanup. I haven't looked in there to see if it can be extended to solve the problems we've seen.

Here are some examples of potential vector/scalar enhancements that we've been collectively chasing (for many years now...):

1. Vector load combining: http://llvm.org/PR16739
2. Vector load combining: http://llvm.org/PR21780
3. Vector load combining: http://llvm.org/PR39473
4. Vector store combining: http://llvm.org/PR41892
5. Insert/extract -> shuffle combining: http://llvm.org/PR34724
6. Compare insert/extract: http://llvm.org/PR39665
7. Compare insert/extract: http://llvm.org/PR43745 (Failed to get SLP to do this so far.)
8. Binop insert/extract: http://llvm.org/PR42633 (I suggested a pass like this proposal in this bug report.)
9. This is going in the opposite direction, but here's a questionable (because it might interfere with GVN) scalarization proposal for InstCombine: D71828 <https://reviews.llvm.org/D71828>
10. Similarly, I proposed a scalarization for binops in InstCombine that's hard to justify without TTI: D50992 <https://reviews.llvm.org/D50992>
11. Shuffle fold that was too dangerous for InstCombine, but should be fine with TTI: D31509 <https://reviews.llvm.org/D31509>


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