[llvm] 3f8916b - [SelectionDAG] ComputeNumSignBits - add support for rotate non-uniform vector amounts

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-01-25T19:15:05Z
New Revision: 3f8916b2e8989e5f77216f20cf44f10a0e3e12e5

URL: https://github.com/llvm/llvm-project/commit/3f8916b2e8989e5f77216f20cf44f10a0e3e12e5
DIFF: https://github.com/llvm/llvm-project/commit/3f8916b2e8989e5f77216f20cf44f10a0e3e12e5.diff

LOG: [SelectionDAG] ComputeNumSignBits - add support for rotate non-uniform vector amounts

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/test/CodeGen/X86/rotate_vec.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 392243379f5a..4d8977856d27 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3749,7 +3749,8 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
     if (Tmp == VTBits)
       return VTBits;
 
-    if (ConstantSDNode *C = isConstOrConstSplat(Op.getOperand(1))) {
+    if (ConstantSDNode *C =
+            isConstOrConstSplat(Op.getOperand(1), DemandedElts)) {
       unsigned RotAmt = C->getAPIntValue().urem(VTBits);
 
       // Handle rotate right by N like a rotate left by 32-N.

diff  --git a/llvm/test/CodeGen/X86/rotate_vec.ll b/llvm/test/CodeGen/X86/rotate_vec.ll
index 66a108333cce..d2d646248616 100644
--- a/llvm/test/CodeGen/X86/rotate_vec.ll
+++ b/llvm/test/CodeGen/X86/rotate_vec.ll
@@ -121,20 +121,16 @@ define <4 x i32> @rot_v4i32_mask_ashr1(<4 x i32> %a0) {
 ; XOP-LABEL: rot_v4i32_mask_ashr1:
 ; XOP:       # %bb.0:
 ; XOP-NEXT:    vpsrad $25, %xmm0, %xmm0
-; XOP-NEXT:    vmovdqa {{.*#+}} xmm1 = [1,2,3,4]
-; XOP-NEXT:    vprotd %xmm1, %xmm0, %xmm0
+; XOP-NEXT:    vprotd $1, %xmm0, %xmm0
 ; XOP-NEXT:    vpbroadcastd %xmm0, %xmm0
-; XOP-NEXT:    vpsravd %xmm1, %xmm0, %xmm0
 ; XOP-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
 ; XOP-NEXT:    retq
 ;
 ; AVX512-LABEL: rot_v4i32_mask_ashr1:
 ; AVX512:       # %bb.0:
-; AVX512-NEXT:    vmovdqa {{.*#+}} xmm1 = [1,2,3,4]
 ; AVX512-NEXT:    vpsrad $25, %xmm0, %xmm0
-; AVX512-NEXT:    vprolvd %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vprold $1, %xmm0, %xmm0
 ; AVX512-NEXT:    vpbroadcastd %xmm0, %xmm0
-; AVX512-NEXT:    vpsravd %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
 ; AVX512-NEXT:    retq
   %1 = ashr <4 x i32> %a0, <i32 25, i32 26, i32 27, i32 28>