[PATCH] D73382: AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: nhaehnle, kerbowa.
Herald added subscribers: Petar.Avramovic, hiraditya, t-tye, tpr, dstuttard, rovka, yaxunl, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

If we have s_pack_* instructions, legalize this to
G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the
s_pack_* instructions really behave.

      

If we don't have s_pack_ instructions, expand this by creating a merge
to s32 and bitcasting. This expands to the expected bit operations. I
think this eventually should go in a new bitcast legalize action type
in LegalizerHelper.

      

We already directly emit the shift operations in RegBankSelect for the
vector case. This could possibly be cleaned up, but I also may want to
defer doing this expansion to selection anyway. I'll see about that
when I try to actually match VOP3P instructions.

      

This breaks the selection of the build_vector since tablegen doesn't
know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.


https://reviews.llvm.org/D73382

Files:
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector-trunc.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.v2s16.mir