[PATCH] D73375: AMDGPU/GlobalISel: Fix tablegen selection for scalar bin ops

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: nhaehnle, kerbowa, rampitec, kzhuravl.
Herald added subscribers: Petar.Avramovic, hiraditya, t-tye, tpr, dstuttard, rovka, yaxunl, wdng, jvesely.
Herald added a project: LLVM.
arsenm added a parent revision: D73372: Revert "AMDGPU: Temporary drop s_mul_hi_i/u32 patterns".

Fixes selection for scalar G_SMULH/G_UMULH. Also switches to using
tablegen selected add/sub, which switch to the signed version of the
opcode. This matches the current DAG behavior. We can't drop the
manual selection for add/sub yet, because it's still both for VALU
add/sub and for G_PTR_ADD.


https://reviews.llvm.org/D73375

Files:
  llvm/lib/Target/AMDGPU/SOPInstructions.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir

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