[PATCH] D73321: AMDPGPU/GlobalISel: Select more MUBUF global addressing modes

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: nhaehnle, kerbowa.
Herald added subscribers: Petar.Avramovic, jfb, hiraditya, rovka, wdng, jvesely.
Herald added a project: LLVM.

The handling of the high bits of the resource descriptor seem weird to
me, where the 3rd dword changes based on the instruction.


https://reviews.llvm.org/D73321

Files:
  llvm/lib/Target/AMDGPU/AMDGPUGISel.td
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D73321.240083.patch
Type: text/x-patch
Size: 169286 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200124/b51f5f20/attachment-0001.bin>