[llvm] f2ccd5a - [AArch64][test] Fix MC/AArch64 tests after D72799

[Fangrui Song via llvm-commits]

Author: Fangrui Song
Date: 2020-01-23T10:47:50-08:00
New Revision: f2ccd5a956cd36141e1ea001f4e1dce359d949c5

URL: https://github.com/llvm/llvm-project/commit/f2ccd5a956cd36141e1ea001f4e1dce359d949c5
DIFF: https://github.com/llvm/llvm-project/commit/f2ccd5a956cd36141e1ea001f4e1dce359d949c5.diff

LOG: [AArch64][test] Fix MC/AArch64 tests after D72799

Added: 
    

Modified: 
    llvm/test/MC/AArch64/ete-sysregs.s
    llvm/test/MC/AArch64/trace-regs.s

Removed: 
    


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diff  --git a/llvm/test/MC/AArch64/ete-sysregs.s b/llvm/test/MC/AArch64/ete-sysregs.s
index 5d5d7282fd64..5d0d293f2d54 100644
--- a/llvm/test/MC/AArch64/ete-sysregs.s
+++ b/llvm/test/MC/AArch64/ete-sysregs.s
@@ -11,8 +11,8 @@ mrs x0, TRCEXTINSELR2
 mrs x0, TRCEXTINSELR3
 
 // CHECK: mrs x0, TRCRSR        // encoding: [0x00,0x0a,0x31,0xd5]
-// CHECK: mrs x0, TRCEXTINSELR  // encoding: [0x80,0x08,0x31,0xd5]
-// CHECK: mrs x0, TRCEXTINSELR  // encoding: [0x80,0x08,0x31,0xd5]
+// CHECK: mrs x0, TRCEXTINSELR0 // encoding: [0x80,0x08,0x31,0xd5]
+// CHECK: mrs x0, TRCEXTINSELR0 // encoding: [0x80,0x08,0x31,0xd5]
 // CHECK: mrs x0, TRCEXTINSELR1 // encoding: [0x80,0x09,0x31,0xd5]
 // CHECK: mrs x0, TRCEXTINSELR2 // encoding: [0x80,0x0a,0x31,0xd5]
 // CHECK: mrs x0, TRCEXTINSELR3 // encoding: [0x80,0x0b,0x31,0xd5]
@@ -26,8 +26,8 @@ msr TRCEXTINSELR2, x0
 msr TRCEXTINSELR3, x0
 
 // CHECK: msr TRCRSR, x0        // encoding: [0x00,0x0a,0x11,0xd5]
-// CHECK: msr TRCEXTINSELR,  x0 // encoding: [0x80,0x08,0x11,0xd5]
-// CHECK: msr TRCEXTINSELR,  x0 // encoding: [0x80,0x08,0x11,0xd5]
+// CHECK: msr TRCEXTINSELR0, x0 // encoding: [0x80,0x08,0x11,0xd5]
+// CHECK: msr TRCEXTINSELR0, x0 // encoding: [0x80,0x08,0x11,0xd5]
 // CHECK: msr TRCEXTINSELR1, x0 // encoding: [0x80,0x09,0x11,0xd5]
 // CHECK: msr TRCEXTINSELR2, x0 // encoding: [0x80,0x0a,0x11,0xd5]
 // CHECK: msr TRCEXTINSELR3, x0 // encoding: [0x80,0x0b,0x11,0xd5]

diff  --git a/llvm/test/MC/AArch64/trace-regs.s b/llvm/test/MC/AArch64/trace-regs.s
index 92f16cd54f31..25738ddd6491 100644
--- a/llvm/test/MC/AArch64/trace-regs.s
+++ b/llvm/test/MC/AArch64/trace-regs.s
@@ -269,7 +269,7 @@
 // CHECK: mrs      x26, {{trcseqevr2|TRCSEQEVR2}}            // encoding: [0x9a,0x02,0x31,0xd5]
 // CHECK: mrs      x14, {{trcseqrstevr|TRCSEQRSTEVR}}          // encoding: [0x8e,0x06,0x31,0xd5]
 // CHECK: mrs      x4, {{trcseqstr|TRCSEQSTR}}              // encoding: [0x84,0x07,0x31,0xd5]
-// CHECK: mrs      x17, {{trcextinselr|TRCEXTINSELR}}          // encoding: [0x91,0x08,0x31,0xd5]
+// CHECK: mrs      x17, {{trcextinselr|TRCEXTINSELR0}}         // encoding: [0x91,0x08,0x31,0xd5]
 // CHECK: mrs      x21, {{trccntrldvr0|TRCCNTRLDVR0}}          // encoding: [0xb5,0x00,0x31,0xd5]
 // CHECK: mrs      x10, {{trccntrldvr1|TRCCNTRLDVR1}}          // encoding: [0xaa,0x01,0x31,0xd5]
 // CHECK: mrs      x20, {{trccntrldvr2|TRCCNTRLDVR2}}          // encoding: [0xb4,0x02,0x31,0xd5]
@@ -618,7 +618,7 @@
 // CHECK: msr      {{trcseqevr2|TRCSEQEVR2}}, x16            // encoding: [0x90,0x02,0x11,0xd5]
 // CHECK: msr      {{trcseqrstevr|TRCSEQRSTEVR}}, x16          // encoding: [0x90,0x06,0x11,0xd5]
 // CHECK: msr      {{trcseqstr|TRCSEQSTR}}, x25             // encoding: [0x99,0x07,0x11,0xd5]
-// CHECK: msr      {{trcextinselr|TRCEXTINSELR}}, x29          // encoding: [0x9d,0x08,0x11,0xd5]
+// CHECK: msr      {{trcextinselr|TRCEXTINSELR0}}, x29         // encoding: [0x9d,0x08,0x11,0xd5]
 // CHECK: msr      {{trccntrldvr0|TRCCNTRLDVR0}}, x20          // encoding: [0xb4,0x00,0x11,0xd5]
 // CHECK: msr      {{trccntrldvr1|TRCCNTRLDVR1}}, x20          // encoding: [0xb4,0x01,0x11,0xd5]
 // CHECK: msr      {{trccntrldvr2|TRCCNTRLDVR2}}, x22          // encoding: [0xb6,0x02,0x11,0xd5]