[PATCH] D73132: Allow combining of extract_subvector to extract element

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec marked an inline comment as done.
rampitec added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:18573-18574
+          }
+          if (NewExtNumElts == 1 &&
+              TLI.isOperationLegalOrCustom(ISD::EXTRACT_VECTOR_ELT, ScalarVT)) {
+            SDValue NewIndex = DAG.getVectorIdxConstant(IndexValScaled, DL);
----------------
rampitec wrote:
> lebedev.ri wrote:
> > I'm guessing the order doesn't matter?
> > If `ISD::EXTRACT_VECTOR_ELT` is legal, we'll transform
> > single-element `ISD::EXTRACT_SUBVECTOR` into `ISD::EXTRACT_VECTOR_ELT` later anyway?
> > 
> Unfortunately it matters. ARM makes legal v1i32  but does worse job for i32. If I change the order that leads to obvious regression in ARM Neon.
Sorry, it is aarch64, not arm.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73132/new/

https://reviews.llvm.org/D73132