[PATCH] D73132: Allow combining of extract_subvector to extract element

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri accepted this revision.
lebedev.ri added reviewers: spatel, deadalnix.
lebedev.ri added a comment.
This revision is now accepted and ready to land.

This LG to me.



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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:18561-18567
+        EVT ScalarVT = SrcVT.getScalarType();
+        if ((N->getConstantOperandVal(1) % DestSrcRatio) == 0) {
           SDLoc DL(N);
-          SDValue NewIndex = DAG.getVectorIdxConstant(IndexValScaled, DL);
-          SDValue NewExtract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NewExtVT,
-                                           V.getOperand(0), NewIndex);
-          return DAG.getBitcast(NVT, NewExtract);
+          unsigned IndexValScaled = N->getConstantOperandVal(1) / DestSrcRatio;
+          EVT NewExtVT = EVT::getVectorVT(*DAG.getContext(),
+                                          ScalarVT, NewExtNumElts);
+          if (TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NewExtVT)) {
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Can you precommit this NFC part?


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:18573-18574
+          }
+          if (NewExtNumElts == 1 &&
+              TLI.isOperationLegalOrCustom(ISD::EXTRACT_VECTOR_ELT, ScalarVT)) {
+            SDValue NewIndex = DAG.getVectorIdxConstant(IndexValScaled, DL);
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I'm guessing the order doesn't matter?
If `ISD::EXTRACT_VECTOR_ELT` is legal, we'll transform
single-element `ISD::EXTRACT_SUBVECTOR` into `ISD::EXTRACT_VECTOR_ELT` later anyway?



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  https://reviews.llvm.org/D73132/new/

https://reviews.llvm.org/D73132