[PATCH] D73197: [x86] match concat of 128-bit high half vectors before lowering to VPERM2X128

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: lebedev.ri, RKSimon, craig.topper.
Herald added subscribers: hiraditya, mcrosier.
Herald added a project: LLVM.

shuffle (ins ?, X, C1), (ins ?, Y, C2), Mask --> concat X, Y

This is another shuffle problem seen with PR42024:
https://bugs.llvm.org/show_bug.cgi?id=42024

We have this small crack in legalization/lowering/combining/demanded that allows forming a vperm2f128 of high halves with AVX1 when we could do better by peeking through the insert_subvector nodes. AFAICT, it requires IR as shown in the diffs - much larger than legal vectors - to avoid all of the usual folds.

Another option might be to allow forming the 256-bit vperm here and then doing custom shuffle combining on that opcode.


https://reviews.llvm.org/D73197

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/x86-interleaved-access.ll

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