[llvm] f04284c - [TargetLowering] SimplifyDemandedBits ISD::SRA multi-use handling

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-01-21T15:12:07Z
New Revision: f04284cf1d491a5d9a1eebfd14ed2eb6342f5e47

URL: https://github.com/llvm/llvm-project/commit/f04284cf1d491a5d9a1eebfd14ed2eb6342f5e47
DIFF: https://github.com/llvm/llvm-project/commit/f04284cf1d491a5d9a1eebfd14ed2eb6342f5e47.diff

LOG: [TargetLowering] SimplifyDemandedBits ISD::SRA multi-use handling

Call SimplifyMultipleUseDemandedBits to peek through extended source args with multiple uses

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/test/CodeGen/X86/const-shift-of-constmasked.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 4cd907224d8e..9ae331b65c14 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1534,6 +1534,16 @@ bool TargetLowering::SimplifyDemandedBits(
       if (Known.One[BitWidth - ShAmt - 1])
         // New bits are known one.
         Known.One.setHighBits(ShAmt);
+
+      // Attempt to avoid multi-use ops if we don't need anything from them.
+      if (!InDemandedMask.isAllOnesValue() || !DemandedElts.isAllOnesValue()) {
+        SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
+            Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1);
+        if (DemandedOp0) {
+          SDValue NewOp = TLO.DAG.getNode(ISD::SRA, dl, VT, DemandedOp0, Op1);
+          return TLO.CombineTo(Op, NewOp);
+        }
+      }
     }
     break;
   }

diff  --git a/llvm/test/CodeGen/X86/const-shift-of-constmasked.ll b/llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
index 08ef7403af8a..e52b3af2fe10 100644
--- a/llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
+++ b/llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
@@ -1870,9 +1870,9 @@ define i64 @test_i64_18446744065119617024_mask_ashr_1(i64 %a0) {
 define i64 @test_i64_18446744065119617024_mask_ashr_32(i64 %a0) {
 ; X32-LABEL: test_i64_18446744065119617024_mask_ashr_32:
 ; X32:       # %bb.0:
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    movl %edx, %eax
 ; X32-NEXT:    andl $-2, %eax
-; X32-NEXT:    movl %eax, %edx
 ; X32-NEXT:    sarl $31, %edx
 ; X32-NEXT:    retl
 ;