[llvm] 317fdcd - AMDGPU: Cleanup and generate 64-bit div tests
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 20 14:52:07 PST 2020
Author: Matt Arsenault
Date: 2020-01-20T17:19:39-05:00
New Revision: 317fdcd09ae9df1eaf1da40443d59b8b2bf68b8b
URL: https://github.com/llvm/llvm-project/commit/317fdcd09ae9df1eaf1da40443d59b8b2bf68b8b
DIFF: https://github.com/llvm/llvm-project/commit/317fdcd09ae9df1eaf1da40443d59b8b2bf68b8b.diff
LOG: AMDGPU: Cleanup and generate 64-bit div tests
Split out r600 tests, and try to be more consistent with
coverage. Cover a few more cases for 24-bit optimization and
constants.
Added:
llvm/test/CodeGen/AMDGPU/sdiv64.ll
llvm/test/CodeGen/AMDGPU/sdivrem64.r600.ll
llvm/test/CodeGen/AMDGPU/srem64.ll
llvm/test/CodeGen/AMDGPU/udiv64.ll
llvm/test/CodeGen/AMDGPU/udivrem64.r600.ll
llvm/test/CodeGen/AMDGPU/urem64.ll
Modified:
Removed:
llvm/test/CodeGen/AMDGPU/sdivrem64.ll
llvm/test/CodeGen/AMDGPU/udivrem64.ll
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
new file mode 100644
index 000000000000..386d4b944406
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
@@ -0,0 +1,1165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_sdiv:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_ashr_i32 s0, s3, 31
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_mov_b32 s4, s8
+; GCN-NEXT: s_mov_b32 s5, s9
+; GCN-NEXT: s_mov_b32 s1, s0
+; GCN-NEXT: s_add_u32 s2, s2, s0
+; GCN-NEXT: s_addc_u32 s3, s3, s0
+; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1]
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3
+; GCN-NEXT: s_sub_u32 s14, 0, s2
+; GCN-NEXT: v_mov_b32_e32 v4, s3
+; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; GCN-NEXT: s_subb_u32 s15, 0, s3
+; GCN-NEXT: s_ashr_i32 s8, s11, 31
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
+; GCN-NEXT: s_mov_b32 s9, s8
+; GCN-NEXT: s_add_u32 s10, s10, s8
+; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
+; GCN-NEXT: s_addc_u32 s11, s11, s8
+; GCN-NEXT: s_xor_b64 s[12:13], s[8:9], s[0:1]
+; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; GCN-NEXT: s_xor_b64 s[8:9], s[10:11], s[8:9]
+; GCN-NEXT: v_mov_b32_e32 v5, s13
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mov_b32_e32 v6, s9
+; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_lo_u32 v7, s14, v3
+; GCN-NEXT: v_mul_lo_u32 v8, s15, v2
+; GCN-NEXT: v_mul_hi_u32 v9, s14, v2
+; GCN-NEXT: v_mul_lo_u32 v10, s14, v2
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7
+; GCN-NEXT: v_mul_hi_u32 v9, v2, v10
+; GCN-NEXT: v_mul_hi_u32 v11, v3, v10
+; GCN-NEXT: v_mul_lo_u32 v10, v3, v10
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GCN-NEXT: v_mul_hi_u32 v8, v2, v7
+; GCN-NEXT: v_mul_lo_u32 v12, v2, v7
+; GCN-NEXT: v_mul_hi_u32 v13, v3, v7
+; GCN-NEXT: v_mul_lo_u32 v7, v3, v7
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v11, vcc
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v9, vcc
+; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v7
+; GCN-NEXT: v_addc_u32_e64 v7, vcc, v3, v8, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v9, s14, v2
+; GCN-NEXT: v_mul_lo_u32 v10, s15, v2
+; GCN-NEXT: v_mul_lo_u32 v11, s14, v2
+; GCN-NEXT: v_mul_lo_u32 v12, s14, v7
+; GCN-NEXT: v_mul_hi_u32 v13, v7, v11
+; GCN-NEXT: v_mul_lo_u32 v14, v7, v11
+; GCN-NEXT: v_mul_hi_u32 v11, v2, v11
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT: v_mul_hi_u32 v10, v7, v9
+; GCN-NEXT: v_mul_hi_u32 v12, v2, v9
+; GCN-NEXT: v_mul_lo_u32 v15, v2, v9
+; GCN-NEXT: v_mul_lo_u32 v7, v7, v9
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v15
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v1, v12, vcc
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v14, v9
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v13, vcc
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v8
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v10, vcc
+; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v8, s[0:1]
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v7, s8, v2
+; GCN-NEXT: v_mul_hi_u32 v8, s9, v2
+; GCN-NEXT: v_mul_lo_u32 v2, s9, v2
+; GCN-NEXT: v_mul_hi_u32 v9, s8, v3
+; GCN-NEXT: v_mul_lo_u32 v10, s8, v3
+; GCN-NEXT: v_mul_hi_u32 v11, s9, v3
+; GCN-NEXT: v_mul_lo_u32 v3, s9, v3
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v1, v9, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v8, vcc
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v11, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc
+; GCN-NEXT: v_mul_hi_u32 v1, s2, v2
+; GCN-NEXT: v_mul_lo_u32 v3, s3, v2
+; GCN-NEXT: v_mul_lo_u32 v7, s2, v2
+; GCN-NEXT: v_mul_lo_u32 v8, s2, v0
+; GCN-NEXT: v_add_i32_e32 v9, vcc, 2, v2
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v2
+; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v8
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, s9, v1
+; GCN-NEXT: v_sub_i32_e32 v7, vcc, s8, v7
+; GCN-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
+; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s2, v7
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v6, v1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v7
+; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GCN-NEXT: v_subbrev_u32_e64 v3, vcc, 0, v3, s[0:1]
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v4
+; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
+; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v4, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v12, v10, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v1, v11, v9, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[0:1]
+; GCN-NEXT: v_xor_b32_e32 v2, s13, v0
+; GCN-NEXT: v_xor_b32_e32 v0, s12, v1
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v2, v5, vcc
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %result = sdiv i64 %x, %y
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define i64 @v_test_sdiv(i64 %x, i64 %y) {
+; GCN-LABEL: v_test_sdiv:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GCN-NEXT: v_mov_b32_e32 v5, 0
+; GCN-NEXT: v_mov_b32_e32 v6, 0
+; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v1
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v7
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc
+; GCN-NEXT: v_xor_b32_e32 v8, v7, v4
+; GCN-NEXT: v_xor_b32_e32 v3, v3, v4
+; GCN-NEXT: v_xor_b32_e32 v2, v2, v4
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v7
+; GCN-NEXT: v_xor_b32_e32 v0, v0, v7
+; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2
+; GCN-NEXT: v_cvt_f32_u32_e32 v7, v3
+; GCN-NEXT: v_sub_i32_e32 v9, vcc, 0, v2
+; GCN-NEXT: v_subb_u32_e32 v10, vcc, 0, v3, vcc
+; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v7
+; GCN-NEXT: v_rcp_f32_e32 v4, v4
+; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GCN-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4
+; GCN-NEXT: v_trunc_f32_e32 v7, v7
+; GCN-NEXT: v_mac_f32_e32 v4, 0xcf800000, v7
+; GCN-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GCN-NEXT: v_mul_lo_u32 v11, v9, v7
+; GCN-NEXT: v_mul_lo_u32 v12, v10, v4
+; GCN-NEXT: v_mul_hi_u32 v13, v9, v4
+; GCN-NEXT: v_mul_lo_u32 v14, v9, v4
+; GCN-NEXT: v_add_i32_e32 v11, vcc, v13, v11
+; GCN-NEXT: v_mul_hi_u32 v13, v4, v14
+; GCN-NEXT: v_mul_hi_u32 v15, v7, v14
+; GCN-NEXT: v_mul_lo_u32 v14, v7, v14
+; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12
+; GCN-NEXT: v_mul_hi_u32 v12, v4, v11
+; GCN-NEXT: v_mul_lo_u32 v16, v4, v11
+; GCN-NEXT: v_mul_hi_u32 v17, v7, v11
+; GCN-NEXT: v_mul_lo_u32 v11, v7, v11
+; GCN-NEXT: v_add_i32_e32 v13, vcc, v13, v16
+; GCN-NEXT: v_addc_u32_e32 v12, vcc, v6, v12, vcc
+; GCN-NEXT: v_add_i32_e32 v13, vcc, v14, v13
+; GCN-NEXT: v_addc_u32_e32 v12, vcc, v12, v15, vcc
+; GCN-NEXT: v_addc_u32_e32 v13, vcc, v17, v5, vcc
+; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11
+; GCN-NEXT: v_addc_u32_e32 v12, vcc, v6, v13, vcc
+; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v11
+; GCN-NEXT: v_addc_u32_e64 v11, vcc, v7, v12, s[4:5]
+; GCN-NEXT: v_mul_hi_u32 v13, v9, v4
+; GCN-NEXT: v_mul_lo_u32 v10, v10, v4
+; GCN-NEXT: v_mul_lo_u32 v14, v9, v4
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v12
+; GCN-NEXT: v_mul_lo_u32 v9, v9, v11
+; GCN-NEXT: v_mul_hi_u32 v12, v11, v14
+; GCN-NEXT: v_mul_lo_u32 v15, v11, v14
+; GCN-NEXT: v_mul_hi_u32 v14, v4, v14
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v13, v9
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10
+; GCN-NEXT: v_mul_hi_u32 v10, v11, v9
+; GCN-NEXT: v_mul_hi_u32 v13, v4, v9
+; GCN-NEXT: v_mul_lo_u32 v16, v4, v9
+; GCN-NEXT: v_mul_lo_u32 v9, v11, v9
+; GCN-NEXT: v_add_i32_e32 v11, vcc, v14, v16
+; GCN-NEXT: v_addc_u32_e32 v13, vcc, v6, v13, vcc
+; GCN-NEXT: v_add_i32_e32 v11, vcc, v15, v11
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v13, v12, vcc
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v5, vcc
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v9
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v6, v10, vcc
+; GCN-NEXT: v_addc_u32_e64 v7, vcc, v7, v10, s[4:5]
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v9
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
+; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
+; GCN-NEXT: v_mul_hi_u32 v10, v1, v4
+; GCN-NEXT: v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT: v_mul_hi_u32 v11, v0, v7
+; GCN-NEXT: v_mul_lo_u32 v12, v0, v7
+; GCN-NEXT: v_mul_hi_u32 v13, v1, v7
+; GCN-NEXT: v_mul_lo_u32 v7, v1, v7
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v6, v11, vcc
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v9
+; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v10, vcc
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, v13, v5, vcc
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
+; GCN-NEXT: v_mul_lo_u32 v7, v3, v4
+; GCN-NEXT: v_mul_lo_u32 v9, v2, v4
+; GCN-NEXT: v_mul_lo_u32 v10, v2, v5
+; GCN-NEXT: v_add_i32_e32 v11, vcc, 2, v4
+; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v5, vcc
+; GCN-NEXT: v_add_i32_e32 v13, vcc, 1, v4
+; GCN-NEXT: v_addc_u32_e32 v14, vcc, 0, v5, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GCN-NEXT: v_sub_i32_e32 v7, vcc, v1, v6
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v9
+; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v7, v3, vcc
+; GCN-NEXT: v_sub_i32_e64 v9, s[4:5], v0, v2
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
+; GCN-NEXT: v_subbrev_u32_e64 v6, vcc, 0, v7, s[4:5]
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v9, v2
+; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
+; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v3
+; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v6, v3
+; GCN-NEXT: v_cndmask_b32_e32 v1, v9, v2, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v14, v12, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v5, v1, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v1, v13, v11, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]
+; GCN-NEXT: v_xor_b32_e32 v2, v0, v8
+; GCN-NEXT: v_xor_b32_e32 v0, v1, v8
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v2, v8, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = sdiv i64 %x, %y
+ ret i64 %result
+}
+
+define amdgpu_kernel void @s_test_sdiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_sdiv24_64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s9, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s3, 0xf000
+; GCN-NEXT: s_mov_b32 s2, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s0, s4
+; GCN-NEXT: s_mov_b32 s1, s5
+; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 40
+; GCN-NEXT: s_ashr_i64 s[6:7], s[8:9], 40
+; GCN-NEXT: s_xor_b32 s5, s4, s6
+; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6
+; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4
+; GCN-NEXT: s_ashr_i32 s4, s5, 30
+; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GCN-NEXT: s_or_b32 s4, s4, 1
+; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
+; GCN-NEXT: v_trunc_f32_e32 v2, v2
+; GCN-NEXT: v_mov_b32_e32 v3, s4
+; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GCN-NEXT: v_cvt_i32_f32_e32 v1, v2
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-NEXT: s_endpgm
+ %1 = ashr i64 %x, 40
+ %2 = ashr i64 %y, 40
+ %result = sdiv i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define i64 @v_test_sdiv24_64(i64 %x, i64 %y) {
+; GCN-LABEL: v_test_sdiv24_64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
+; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, v1
+; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_hi_u32 v3, v2, v1
+; GCN-NEXT: v_mul_lo_u32 v4, v2, v1
+; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v4
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GCN-NEXT: v_mul_hi_u32 v3, v3, v2
+; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v2, v3
+; GCN-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v3
+; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GCN-NEXT: v_mul_hi_u32 v2, v2, v0
+; GCN-NEXT: v_mul_lo_u32 v3, v2, v1
+; GCN-NEXT: v_add_i32_e32 v4, vcc, 1, v2
+; GCN-NEXT: v_add_i32_e32 v5, vcc, -1, v2
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
+; GCN-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v3
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v1
+; GCN-NEXT: s_and_b64 s[4:5], s[4:5], vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %1 = lshr i64 %x, 40
+ %2 = lshr i64 %y, 40
+ %result = sdiv i64 %1, %2
+ ret i64 %result
+}
+
+define amdgpu_kernel void @s_test_sdiv32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_sdiv32_64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s2, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s11, 0xf000
+; GCN-NEXT: s_mov_b32 s10, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s8, s4
+; GCN-NEXT: s_mov_b32 s9, s5
+; GCN-NEXT: s_ashr_i32 s3, s2, 31
+; GCN-NEXT: s_ashr_i32 s4, s7, 31
+; GCN-NEXT: s_add_i32 s2, s2, s3
+; GCN-NEXT: s_add_i32 s0, s7, s4
+; GCN-NEXT: s_xor_b32 s5, s2, s3
+; GCN-NEXT: s_xor_b32 s2, s0, s4
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s5
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s5
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s2
+; GCN-NEXT: v_mul_lo_u32 v1, v0, s5
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s2, v1
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
+; GCN-NEXT: s_and_b64 vcc, vcc, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1]
+; GCN-NEXT: s_xor_b32 s0, s4, s3
+; GCN-NEXT: v_xor_b32_e32 v0, s0, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GCN-NEXT: s_endpgm
+ %1 = ashr i64 %x, 32
+ %2 = ashr i64 %y, 32
+ %result = sdiv i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_sdiv31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_sdiv31_64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s3, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s11, 0xf000
+; GCN-NEXT: s_mov_b32 s10, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s8, s4
+; GCN-NEXT: s_mov_b32 s9, s5
+; GCN-NEXT: s_ashr_i64 s[0:1], s[6:7], 33
+; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 33
+; GCN-NEXT: s_ashr_i32 s3, s2, 31
+; GCN-NEXT: s_ashr_i32 s4, s0, 31
+; GCN-NEXT: s_add_i32 s1, s2, s3
+; GCN-NEXT: s_add_i32 s0, s0, s4
+; GCN-NEXT: s_xor_b32 s5, s1, s3
+; GCN-NEXT: s_xor_b32 s2, s0, s4
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s5
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s5
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s2
+; GCN-NEXT: v_mul_lo_u32 v1, v0, s5
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s2, v1
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
+; GCN-NEXT: s_and_b64 vcc, vcc, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1]
+; GCN-NEXT: s_xor_b32 s0, s4, s3
+; GCN-NEXT: v_xor_b32_e32 v0, s0, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GCN-NEXT: s_endpgm
+ %1 = ashr i64 %x, 33
+ %2 = ashr i64 %y, 33
+ %result = sdiv i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_sdiv23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_sdiv23_64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s9, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s3, 0xf000
+; GCN-NEXT: s_mov_b32 s2, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s0, s4
+; GCN-NEXT: s_mov_b32 s1, s5
+; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 41
+; GCN-NEXT: s_ashr_i64 s[6:7], s[8:9], 41
+; GCN-NEXT: s_xor_b32 s5, s4, s6
+; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6
+; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4
+; GCN-NEXT: s_ashr_i32 s4, s5, 30
+; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GCN-NEXT: s_or_b32 s4, s4, 1
+; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
+; GCN-NEXT: v_trunc_f32_e32 v2, v2
+; GCN-NEXT: v_mov_b32_e32 v3, s4
+; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GCN-NEXT: v_cvt_i32_f32_e32 v1, v2
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 23
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-NEXT: s_endpgm
+ %1 = ashr i64 %x, 41
+ %2 = ashr i64 %y, 41
+ %result = sdiv i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_sdiv25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_sdiv25_64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s3, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s11, 0xf000
+; GCN-NEXT: s_mov_b32 s10, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s8, s4
+; GCN-NEXT: s_mov_b32 s9, s5
+; GCN-NEXT: s_ashr_i64 s[0:1], s[6:7], 39
+; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 39
+; GCN-NEXT: s_ashr_i32 s3, s2, 31
+; GCN-NEXT: s_ashr_i32 s4, s0, 31
+; GCN-NEXT: s_add_i32 s1, s2, s3
+; GCN-NEXT: s_add_i32 s0, s0, s4
+; GCN-NEXT: s_xor_b32 s5, s1, s3
+; GCN-NEXT: s_xor_b32 s2, s0, s4
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s5
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s5
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s2
+; GCN-NEXT: v_mul_lo_u32 v1, v0, s5
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s2, v1
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
+; GCN-NEXT: s_and_b64 vcc, vcc, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1]
+; GCN-NEXT: s_xor_b32 s0, s4, s3
+; GCN-NEXT: v_xor_b32_e32 v0, s0, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GCN-NEXT: s_endpgm
+ %1 = ashr i64 %x, 39
+ %2 = ashr i64 %y, 39
+ %result = sdiv i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_sdiv24_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
+; GCN-LABEL: s_test_sdiv24_v2i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
+; GCN-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x11
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_ashr_i64 s[0:1], s[8:9], 40
+; GCN-NEXT: s_ashr_i64 s[2:3], s[10:11], 40
+; GCN-NEXT: s_ashr_i64 s[8:9], s[12:13], 40
+; GCN-NEXT: s_ashr_i64 s[10:11], s[14:15], 40
+; GCN-NEXT: s_xor_b32 s1, s2, s10
+; GCN-NEXT: v_cvt_f32_i32_e32 v0, s2
+; GCN-NEXT: v_cvt_f32_i32_e32 v1, s10
+; GCN-NEXT: s_xor_b32 s2, s0, s8
+; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0
+; GCN-NEXT: v_cvt_f32_i32_e32 v3, s8
+; GCN-NEXT: s_ashr_i32 s0, s1, 30
+; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v1
+; GCN-NEXT: s_ashr_i32 s1, s2, 30
+; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v3
+; GCN-NEXT: s_or_b32 s0, s0, 1
+; GCN-NEXT: v_mul_f32_e32 v4, v0, v4
+; GCN-NEXT: s_or_b32 s1, s1, 1
+; GCN-NEXT: v_mul_f32_e32 v5, v2, v5
+; GCN-NEXT: v_trunc_f32_e32 v4, v4
+; GCN-NEXT: v_mov_b32_e32 v6, s0
+; GCN-NEXT: v_trunc_f32_e32 v5, v5
+; GCN-NEXT: v_mov_b32_e32 v7, s1
+; GCN-NEXT: v_mad_f32 v0, -v4, v1, v0
+; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GCN-NEXT: v_mad_f32 v2, -v5, v3, v2
+; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1|
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v3|
+; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v5
+; GCN-NEXT: v_bfe_i32 v2, v0, 0, 24
+; GCN-NEXT: v_bfe_i32 v0, v1, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %1 = ashr <2 x i64> %x, <i64 40, i64 40>
+ %2 = ashr <2 x i64> %y, <i64 40, i64 40>
+ %result = sdiv <2 x i64> %1, %2
+ store <2 x i64> %result, <2 x i64> addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_sdiv24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
+; GCN-LABEL: s_test_sdiv24_48:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s2, s[0:1], 0xb
+; GCN-NEXT: s_load_dword s3, s[0:1], 0xc
+; GCN-NEXT: s_load_dword s8, s[0:1], 0xd
+; GCN-NEXT: s_load_dword s9, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_sext_i32_i16 s0, s3
+; GCN-NEXT: s_sext_i32_i16 s1, s9
+; GCN-NEXT: v_mov_b32_e32 v0, s8
+; GCN-NEXT: v_mov_b32_e32 v1, s2
+; GCN-NEXT: v_alignbit_b32 v0, s1, v0, 24
+; GCN-NEXT: v_alignbit_b32 v1, s0, v1, 24
+; GCN-NEXT: v_xor_b32_e32 v2, v1, v0
+; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v2, 30, v2
+; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GCN-NEXT: v_or_b32_e32 v2, 1, v2
+; GCN-NEXT: v_mul_f32_e32 v3, v1, v3
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mad_f32 v1, -v3, v0, v1
+; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4
+; GCN-NEXT: s_endpgm
+ %1 = ashr i48 %x, 24
+ %2 = ashr i48 %y, 24
+ %result = sdiv i48 %1, %2
+ store i48 %result, i48 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
+; GCN-LABEL: s_test_sdiv_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_ashr_i32 s2, s11, 31
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_mov_b32 s4, s8
+; GCN-NEXT: s_mov_b32 s5, s9
+; GCN-NEXT: s_mov_b32 s3, s2
+; GCN-NEXT: s_add_u32 s0, s10, s2
+; GCN-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NEXT: s_addc_u32 s1, s11, s2
+; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[2:3]
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, s8
+; GCN-NEXT: v_cvt_f32_u32_e32 v4, s9
+; GCN-NEXT: s_sub_u32 s3, 0, s8
+; GCN-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4
+; GCN-NEXT: s_subb_u32 s10, 0, s9
+; GCN-NEXT: v_rcp_f32_e32 v3, v3
+; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3
+; GCN-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
+; GCN-NEXT: v_trunc_f32_e32 v4, v4
+; GCN-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4
+; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_mul_lo_u32 v6, s3, v4
+; GCN-NEXT: v_mul_lo_u32 v7, s10, v3
+; GCN-NEXT: v_mul_hi_u32 v8, s3, v3
+; GCN-NEXT: v_mul_lo_u32 v9, s3, v3
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT: v_mul_hi_u32 v8, v3, v9
+; GCN-NEXT: v_mul_hi_u32 v10, v4, v9
+; GCN-NEXT: v_mul_lo_u32 v9, v4, v9
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GCN-NEXT: v_mul_hi_u32 v7, v3, v6
+; GCN-NEXT: v_mul_lo_u32 v11, v3, v6
+; GCN-NEXT: v_mul_hi_u32 v12, v4, v6
+; GCN-NEXT: v_mul_lo_u32 v6, v4, v6
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v10, vcc
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc
+; GCN-NEXT: v_add_i32_e64 v3, s[0:1], v3, v6
+; GCN-NEXT: v_addc_u32_e64 v6, vcc, v4, v7, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v8, s3, v3
+; GCN-NEXT: v_mul_lo_u32 v9, s10, v3
+; GCN-NEXT: v_mul_lo_u32 v10, s3, v3
+; GCN-NEXT: v_mul_lo_u32 v11, s3, v6
+; GCN-NEXT: v_mul_hi_u32 v12, v6, v10
+; GCN-NEXT: v_mul_lo_u32 v13, v6, v10
+; GCN-NEXT: v_mul_hi_u32 v10, v3, v10
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_mul_hi_u32 v9, v6, v8
+; GCN-NEXT: v_mul_hi_u32 v11, v3, v8
+; GCN-NEXT: v_mul_lo_u32 v14, v3, v8
+; GCN-NEXT: v_mul_lo_u32 v6, v6, v8
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v14
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v1, v11, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v13, v8
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v12, vcc
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v9, vcc
+; GCN-NEXT: v_addc_u32_e64 v4, vcc, v4, v7, s[0:1]
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
+; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, 24, v3
+; GCN-NEXT: v_mul_hi_u32 v3, 0, v3
+; GCN-NEXT: v_mul_hi_u32 v7, 24, v4
+; GCN-NEXT: v_mul_lo_u32 v8, v4, 24
+; GCN-NEXT: v_mul_hi_u32 v4, 0, v4
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, 0, v6
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc
+; GCN-NEXT: v_mul_hi_u32 v3, s8, v1
+; GCN-NEXT: v_mul_lo_u32 v4, s9, v1
+; GCN-NEXT: v_mul_lo_u32 v6, s8, v1
+; GCN-NEXT: v_mul_lo_u32 v7, s8, v0
+; GCN-NEXT: v_add_i32_e32 v8, vcc, 2, v1
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v10, vcc, 1, v1
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
+; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, 24, v6
+; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
+; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s8, v6
+; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v6
+; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GCN-NEXT: v_subbrev_u32_e64 v4, vcc, 0, v4, s[0:1]
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v5
+; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
+; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v4
+; GCN-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v7, v6, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v4
+; GCN-NEXT: v_cndmask_b32_e32 v4, v12, v5, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GCN-NEXT: v_cndmask_b32_e32 v4, v11, v9, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v3, v10, v8, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
+; GCN-NEXT: v_xor_b32_e32 v3, s2, v0
+; GCN-NEXT: v_xor_b32_e32 v0, s2, v1
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %result = sdiv i64 24, %x
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define i64 @v_test_sdiv_k_num_i64(i64 %x) {
+; GCN-LABEL: v_test_sdiv_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GCN-NEXT: v_mov_b32_e32 v3, 0
+; GCN-NEXT: v_mov_b32_e32 v4, 0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v2
+; GCN-NEXT: v_xor_b32_e32 v0, v0, v2
+; GCN-NEXT: v_cvt_f32_u32_e32 v5, v0
+; GCN-NEXT: v_cvt_f32_u32_e32 v6, v1
+; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v0
+; GCN-NEXT: v_subb_u32_e32 v8, vcc, 0, v1, vcc
+; GCN-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
+; GCN-NEXT: v_rcp_f32_e32 v5, v5
+; GCN-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
+; GCN-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
+; GCN-NEXT: v_trunc_f32_e32 v6, v6
+; GCN-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
+; GCN-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GCN-NEXT: v_mul_lo_u32 v9, v7, v6
+; GCN-NEXT: v_mul_lo_u32 v10, v8, v5
+; GCN-NEXT: v_mul_hi_u32 v11, v7, v5
+; GCN-NEXT: v_mul_lo_u32 v12, v7, v5
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v9
+; GCN-NEXT: v_mul_hi_u32 v11, v5, v12
+; GCN-NEXT: v_mul_hi_u32 v13, v6, v12
+; GCN-NEXT: v_mul_lo_u32 v12, v6, v12
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10
+; GCN-NEXT: v_mul_hi_u32 v10, v5, v9
+; GCN-NEXT: v_mul_lo_u32 v14, v5, v9
+; GCN-NEXT: v_mul_hi_u32 v15, v6, v9
+; GCN-NEXT: v_mul_lo_u32 v9, v6, v9
+; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v14
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v10, vcc
+; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v13, vcc
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v15, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v11, vcc
+; GCN-NEXT: v_add_i32_e64 v5, s[4:5], v5, v9
+; GCN-NEXT: v_addc_u32_e64 v9, vcc, v6, v10, s[4:5]
+; GCN-NEXT: v_mul_hi_u32 v11, v7, v5
+; GCN-NEXT: v_mul_lo_u32 v8, v8, v5
+; GCN-NEXT: v_mul_lo_u32 v12, v7, v5
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10
+; GCN-NEXT: v_mul_lo_u32 v7, v7, v9
+; GCN-NEXT: v_mul_hi_u32 v10, v9, v12
+; GCN-NEXT: v_mul_lo_u32 v13, v9, v12
+; GCN-NEXT: v_mul_hi_u32 v12, v5, v12
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v11, v7
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GCN-NEXT: v_mul_hi_u32 v8, v9, v7
+; GCN-NEXT: v_mul_hi_u32 v11, v5, v7
+; GCN-NEXT: v_mul_lo_u32 v14, v5, v7
+; GCN-NEXT: v_mul_lo_u32 v7, v9, v7
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v12, v14
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v4, v11, vcc
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v13, v9
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v10, vcc
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v4, v8, vcc
+; GCN-NEXT: v_addc_u32_e64 v6, vcc, v6, v8, s[4:5]
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; GCN-NEXT: v_mul_hi_u32 v7, 24, v5
+; GCN-NEXT: v_mul_hi_u32 v5, 0, v5
+; GCN-NEXT: v_mul_hi_u32 v8, 24, v6
+; GCN-NEXT: v_mul_lo_u32 v9, v6, 24
+; GCN-NEXT: v_mul_hi_u32 v6, 0, v6
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, 0, v7
+; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v5, v0, v4
+; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
+; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
+; GCN-NEXT: v_mul_lo_u32 v8, v0, v3
+; GCN-NEXT: v_add_i32_e32 v9, vcc, 2, v4
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v4
+; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v5
+; GCN-NEXT: v_sub_i32_e32 v7, vcc, 24, v7
+; GCN-NEXT: v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
+; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v0
+; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v5, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v7, v0
+; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GCN-NEXT: v_subbrev_u32_e64 v6, vcc, 0, v6, s[4:5]
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v8, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
+; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v1
+; GCN-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1
+; GCN-NEXT: v_cndmask_b32_e32 v5, v8, v7, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v6, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v13, v0, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v12, v10, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
+; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v1, v11, v9, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]
+; GCN-NEXT: v_xor_b32_e32 v3, v0, v2
+; GCN-NEXT: v_xor_b32_e32 v0, v1, v2
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = sdiv i64 24, %x
+ ret i64 %result
+}
+
+define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
+; GCN-LABEL: v_test_sdiv_pow2_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GCN-NEXT: v_mov_b32_e32 v3, 0
+; GCN-NEXT: v_mov_b32_e32 v4, 0
+; GCN-NEXT: s_mov_b32 s6, 0x8000
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v2
+; GCN-NEXT: v_xor_b32_e32 v0, v0, v2
+; GCN-NEXT: v_cvt_f32_u32_e32 v5, v0
+; GCN-NEXT: v_cvt_f32_u32_e32 v6, v1
+; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v0
+; GCN-NEXT: v_subb_u32_e32 v8, vcc, 0, v1, vcc
+; GCN-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
+; GCN-NEXT: v_rcp_f32_e32 v5, v5
+; GCN-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
+; GCN-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
+; GCN-NEXT: v_trunc_f32_e32 v6, v6
+; GCN-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
+; GCN-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GCN-NEXT: v_mul_lo_u32 v9, v7, v6
+; GCN-NEXT: v_mul_lo_u32 v10, v8, v5
+; GCN-NEXT: v_mul_hi_u32 v11, v7, v5
+; GCN-NEXT: v_mul_lo_u32 v12, v7, v5
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v9
+; GCN-NEXT: v_mul_hi_u32 v11, v5, v12
+; GCN-NEXT: v_mul_hi_u32 v13, v6, v12
+; GCN-NEXT: v_mul_lo_u32 v12, v6, v12
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10
+; GCN-NEXT: v_mul_hi_u32 v10, v5, v9
+; GCN-NEXT: v_mul_lo_u32 v14, v5, v9
+; GCN-NEXT: v_mul_hi_u32 v15, v6, v9
+; GCN-NEXT: v_mul_lo_u32 v9, v6, v9
+; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v14
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v10, vcc
+; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v13, vcc
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v15, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v11, vcc
+; GCN-NEXT: v_add_i32_e64 v5, s[4:5], v5, v9
+; GCN-NEXT: v_addc_u32_e64 v9, vcc, v6, v10, s[4:5]
+; GCN-NEXT: v_mul_hi_u32 v11, v7, v5
+; GCN-NEXT: v_mul_lo_u32 v8, v8, v5
+; GCN-NEXT: v_mul_lo_u32 v12, v7, v5
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10
+; GCN-NEXT: v_mul_lo_u32 v7, v7, v9
+; GCN-NEXT: v_mul_hi_u32 v10, v9, v12
+; GCN-NEXT: v_mul_lo_u32 v13, v9, v12
+; GCN-NEXT: v_mul_hi_u32 v12, v5, v12
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v11, v7
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GCN-NEXT: v_mul_hi_u32 v8, v9, v7
+; GCN-NEXT: v_mul_hi_u32 v11, v5, v7
+; GCN-NEXT: v_mul_lo_u32 v14, v5, v7
+; GCN-NEXT: v_mul_lo_u32 v7, v9, v7
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v12, v14
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v4, v11, vcc
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v13, v9
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v10, vcc
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v4, v8, vcc
+; GCN-NEXT: v_addc_u32_e64 v6, vcc, v6, v8, s[4:5]
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; GCN-NEXT: v_mul_hi_u32 v7, s6, v5
+; GCN-NEXT: v_mul_hi_u32 v5, 0, v5
+; GCN-NEXT: v_mul_hi_u32 v8, s6, v6
+; GCN-NEXT: v_lshlrev_b32_e32 v9, 15, v6
+; GCN-NEXT: v_mul_hi_u32 v6, 0, v6
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, 0, v7
+; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v5, v0, v4
+; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
+; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
+; GCN-NEXT: v_mul_lo_u32 v8, v0, v3
+; GCN-NEXT: v_add_i32_e32 v9, vcc, 2, v4
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v4
+; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v5
+; GCN-NEXT: v_sub_i32_e32 v7, vcc, s6, v7
+; GCN-NEXT: v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
+; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v0
+; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v5, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v7, v0
+; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GCN-NEXT: v_subbrev_u32_e64 v6, vcc, 0, v6, s[4:5]
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v8, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
+; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v1
+; GCN-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1
+; GCN-NEXT: v_cndmask_b32_e32 v5, v8, v7, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v6, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v13, v0, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v12, v10, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
+; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v1, v11, v9, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]
+; GCN-NEXT: v_xor_b32_e32 v3, v0, v2
+; GCN-NEXT: v_xor_b32_e32 v0, v1, v2
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = sdiv i64 32768, %x
+ ret i64 %result
+}
+
+define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
+; GCN-LABEL: v_test_sdiv_pow2_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 15
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = sdiv i64 %x, 32768
+ ret i64 %result
+}
+
+define amdgpu_kernel void @s_test_sdiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
+; GCN-LABEL: s_test_sdiv24_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s2, 0x41c00000
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: s_ashr_i64 s[0:1], s[2:3], 40
+; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0
+; GCN-NEXT: s_ashr_i32 s0, s0, 30
+; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
+; GCN-NEXT: s_or_b32 s0, s0, 1
+; GCN-NEXT: v_mul_f32_e32 v1, s2, v1
+; GCN-NEXT: v_mov_b32_e32 v2, s0
+; GCN-NEXT: v_trunc_f32_e32 v1, v1
+; GCN-NEXT: v_mad_f32 v3, -v1, v0, s2
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v0|
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %x.shr = ashr i64 %x, 40
+ %result = sdiv i64 24, %x.shr
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_sdiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
+; GCN-LABEL: s_test_sdiv24_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s2, 0x46b6fe00
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: s_ashr_i64 s[0:1], s[2:3], 40
+; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0
+; GCN-NEXT: s_ashr_i32 s0, s0, 30
+; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
+; GCN-NEXT: s_or_b32 s0, s0, 1
+; GCN-NEXT: v_trunc_f32_e32 v1, v1
+; GCN-NEXT: v_mov_b32_e32 v2, s0
+; GCN-NEXT: v_mad_f32 v0, -v1, s2, v0
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %x.shr = ashr i64 %x, 40
+ %result = sdiv i64 %x.shr, 23423
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define i64 @v_test_sdiv24_k_num_i64(i64 %x) {
+; GCN-LABEL: v_test_sdiv24_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
+; GCN-NEXT: s_mov_b32 s4, 0x41c00000
+; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0
+; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
+; GCN-NEXT: v_or_b32_e32 v0, 1, v0
+; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-NEXT: v_trunc_f32_e32 v2, v2
+; GCN-NEXT: v_mad_f32 v3, -v2, v1, s4
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1|
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: v_cvt_i32_f32_e32 v1, v2
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %x.shr = ashr i64 %x, 40
+ %result = sdiv i64 24, %x.shr
+ ret i64 %result
+}
+
+define i64 @v_test_sdiv24_pow2_k_num_i64(i64 %x) {
+; GCN-LABEL: v_test_sdiv24_pow2_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
+; GCN-NEXT: s_mov_b32 s4, 0x47000000
+; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0
+; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
+; GCN-NEXT: v_or_b32_e32 v0, 1, v0
+; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-NEXT: v_trunc_f32_e32 v2, v2
+; GCN-NEXT: v_mad_f32 v3, -v2, v1, s4
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1|
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: v_cvt_i32_f32_e32 v1, v2
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %x.shr = ashr i64 %x, 40
+ %result = sdiv i64 32768, %x.shr
+ ret i64 %result
+}
+
+define i64 @v_test_sdiv24_pow2_k_den_i64(i64 %x) {
+; GCN-LABEL: v_test_sdiv24_pow2_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashr_i64 v[2:3], v[0:1], 40
+; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v1
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 17, v0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 15
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %x.shr = ashr i64 %x, 40
+ %result = sdiv i64 %x.shr, 32768
+ ret i64 %result
+}
diff --git a/llvm/test/CodeGen/AMDGPU/sdivrem64.ll b/llvm/test/CodeGen/AMDGPU/sdivrem64.r600.ll
similarity index 62%
rename from llvm/test/CodeGen/AMDGPU/sdivrem64.ll
rename to llvm/test/CodeGen/AMDGPU/sdivrem64.r600.ll
index d51eededd1c4..db6621da8843 100644
--- a/llvm/test/CodeGen/AMDGPU/sdivrem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdivrem64.r600.ll
@@ -1,8 +1,6 @@
-;RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s
-;RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC %s
-;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
+;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s
-;FUNC-LABEL: {{^}}s_test_sdiv:
+;EG-LABEL: {{^}}s_test_sdiv:
;EG: RECIP_UINT
;EG: LSHL {{.*}}, 1,
;EG: BFE_UINT
@@ -35,21 +33,13 @@
;EG: BFE_UINT
;EG: BFE_UINT
;EG: BFE_UINT
-
-;GCN: v_mac_f32_e32 v{{[0-9]+}}, 0x4f800000,
-;GCN: v_rcp_f32_e32
-;GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x5f7ffffc
-;GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x2f800000
-;GCN: v_trunc_f32_e32
-;GCN: v_mac_f32_e32 v{{[0-9]+}}, 0xcf800000
-;GCN: s_endpgm
define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
%result = sdiv i64 %x, %y
store i64 %result, i64 addrspace(1)* %out
ret void
}
-;FUNC-LABEL: {{^}}s_test_srem:
+;EG-LABEL: {{^}}s_test_srem:
;EG: RECIP_UINT
;EG: BFE_UINT
;EG: BFE_UINT
@@ -82,29 +72,15 @@ define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
;EG: BFE_UINT
;EG: BFE_UINT
;EG: AND_INT {{.*}}, 1,
-
-;GCN: v_mac_f32_e32 v{{[0-9]+}}, 0x4f800000,
-;GCN: v_rcp_f32_e32
-;GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x5f7ffffc
-;GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x2f800000
-;GCN: v_trunc_f32_e32
-;GCN: v_mac_f32_e32 v{{[0-9]+}}, 0xcf800000
-;GCN: s_endpgm
define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
%result = urem i64 %x, %y
store i64 %result, i64 addrspace(1)* %out
ret void
}
-;FUNC-LABEL: {{^}}test_sdiv3264:
+;EG-LABEL: {{^}}test_sdiv3264:
;EG: RECIP_UINT
;EG-NOT: BFE_UINT
-
-;GCN-NOT: s_bfe_u32
-;GCN-NOT: v_mad_f32
-;SI-NOT: v_lshr_b64
-;VI-NOT: v_lshrrev_b64
-;GCN: s_endpgm
define amdgpu_kernel void @test_sdiv3264(i64 addrspace(1)* %out, i64 %x, i64 %y) {
%1 = ashr i64 %x, 33
%2 = ashr i64 %y, 33
@@ -113,15 +89,9 @@ define amdgpu_kernel void @test_sdiv3264(i64 addrspace(1)* %out, i64 %x, i64 %y)
ret void
}
-;FUNC-LABEL: {{^}}test_srem3264:
+;EG-LABEL: {{^}}test_srem3264:
;EG: RECIP_UINT
;EG-NOT: BFE_UINT
-
-;GCN-NOT: s_bfe_u32
-;GCN-NOT: v_mad_f32
-;SI-NOT: v_lshr_b64
-;VI-NOT: v_lshrrev_b64
-;GCN: s_endpgm
define amdgpu_kernel void @test_srem3264(i64 addrspace(1)* %out, i64 %x, i64 %y) {
%1 = ashr i64 %x, 33
%2 = ashr i64 %y, 33
@@ -130,18 +100,12 @@ define amdgpu_kernel void @test_srem3264(i64 addrspace(1)* %out, i64 %x, i64 %y)
ret void
}
-;FUNC-LABEL: {{^}}test_sdiv2464:
+;EG-LABEL: {{^}}test_sdiv2464:
;EG: INT_TO_FLT
;EG: INT_TO_FLT
;EG: FLT_TO_INT
;EG-NOT: RECIP_UINT
;EG-NOT: BFE_UINT
-
-;GCN-NOT: s_bfe_u32
-;GCN: v_mad_f32
-;SI-NOT: v_lshr_b64
-;VI-NOT: v_lshrrev_b64
-;GCN: s_endpgm
define amdgpu_kernel void @test_sdiv2464(i64 addrspace(1)* %out, i64 %x, i64 %y) {
%1 = ashr i64 %x, 40
%2 = ashr i64 %y, 40
@@ -150,18 +114,12 @@ define amdgpu_kernel void @test_sdiv2464(i64 addrspace(1)* %out, i64 %x, i64 %y)
ret void
}
-;FUNC-LABEL: {{^}}test_srem2464:
+;EG-LABEL: {{^}}test_srem2464:
;EG: INT_TO_FLT
;EG: INT_TO_FLT
;EG: FLT_TO_INT
;EG-NOT: RECIP_UINT
;EG-NOT: BFE_UINT
-
-;GCN-NOT: s_bfe_u32
-;GCN: v_mad_f32
-;SI-NOT: v_lshr_b64
-;VI-NOT: v_lshrrev_b64
-;GCN: s_endpgm
define amdgpu_kernel void @test_srem2464(i64 addrspace(1)* %out, i64 %x, i64 %y) {
%1 = ashr i64 %x, 40
%2 = ashr i64 %y, 40
diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll
new file mode 100644
index 000000000000..18824c02edf0
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/srem64.ll
@@ -0,0 +1,1232 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_srem:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s4, s8
+; GCN-NEXT: s_mov_b32 s5, s9
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3
+; GCN-NEXT: s_sub_u32 s8, 0, s2
+; GCN-NEXT: v_mov_b32_e32 v4, s3
+; GCN-NEXT: v_mov_b32_e32 v5, s11
+; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; GCN-NEXT: s_subb_u32 s9, 0, s3
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
+; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_lo_u32 v6, s8, v3
+; GCN-NEXT: v_mul_lo_u32 v7, s9, v2
+; GCN-NEXT: v_mul_hi_u32 v8, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v9, s8, v2
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT: v_mul_hi_u32 v8, v2, v9
+; GCN-NEXT: v_mul_hi_u32 v10, v3, v9
+; GCN-NEXT: v_mul_lo_u32 v9, v3, v9
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GCN-NEXT: v_mul_hi_u32 v7, v2, v6
+; GCN-NEXT: v_mul_lo_u32 v11, v2, v6
+; GCN-NEXT: v_mul_hi_u32 v12, v3, v6
+; GCN-NEXT: v_mul_lo_u32 v6, v3, v6
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v10, vcc
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc
+; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v6
+; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v8, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v9, s9, v2
+; GCN-NEXT: v_mul_lo_u32 v10, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v11, s8, v6
+; GCN-NEXT: v_mul_hi_u32 v12, v6, v10
+; GCN-NEXT: v_mul_lo_u32 v13, v6, v10
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v10
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_mul_hi_u32 v9, v6, v8
+; GCN-NEXT: v_mul_hi_u32 v11, v2, v8
+; GCN-NEXT: v_mul_lo_u32 v14, v2, v8
+; GCN-NEXT: v_mul_lo_u32 v6, v6, v8
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v14
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v1, v11, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v13, v8
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v12, vcc
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v9, vcc
+; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v7, s[0:1]
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, s10, v2
+; GCN-NEXT: v_mul_hi_u32 v7, s11, v2
+; GCN-NEXT: v_mul_lo_u32 v2, s11, v2
+; GCN-NEXT: v_mul_hi_u32 v8, s10, v3
+; GCN-NEXT: v_mul_lo_u32 v9, s10, v3
+; GCN-NEXT: v_mul_hi_u32 v10, s11, v3
+; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v9
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, v8, v7, vcc
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v10, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc
+; GCN-NEXT: v_mul_hi_u32 v1, s2, v2
+; GCN-NEXT: v_mul_lo_u32 v3, s3, v2
+; GCN-NEXT: v_mul_lo_u32 v2, s2, v2
+; GCN-NEXT: v_mul_lo_u32 v0, s2, v0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s11, v0
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, s10, v2
+; GCN-NEXT: v_subb_u32_e64 v1, s[0:1], v1, v4, vcc
+; GCN-NEXT: v_subb_u32_e32 v0, vcc, v5, v0, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
+; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s2, v2
+; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v1, v4, vcc
+; GCN-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v5
+; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v7, vcc, s2, v5
+; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v0
+; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
+; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1]
+; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v0
+; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
+; GCN-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3
+; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %result = urem i64 %x, %y
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define i64 @v_test_srem(i64 %x, i64 %y) {
+; GCN-LABEL: v_test_srem:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GCN-NEXT: v_mov_b32_e32 v5, 0
+; GCN-NEXT: v_mov_b32_e32 v6, 0
+; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v1
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v7
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc
+; GCN-NEXT: v_xor_b32_e32 v3, v3, v4
+; GCN-NEXT: v_xor_b32_e32 v2, v2, v4
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v7
+; GCN-NEXT: v_xor_b32_e32 v0, v0, v7
+; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2
+; GCN-NEXT: v_cvt_f32_u32_e32 v8, v3
+; GCN-NEXT: v_sub_i32_e32 v9, vcc, 0, v2
+; GCN-NEXT: v_subb_u32_e32 v10, vcc, 0, v3, vcc
+; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v8
+; GCN-NEXT: v_rcp_f32_e32 v4, v4
+; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GCN-NEXT: v_mul_f32_e32 v8, 0x2f800000, v4
+; GCN-NEXT: v_trunc_f32_e32 v8, v8
+; GCN-NEXT: v_mac_f32_e32 v4, 0xcf800000, v8
+; GCN-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GCN-NEXT: v_mul_lo_u32 v11, v9, v8
+; GCN-NEXT: v_mul_lo_u32 v12, v10, v4
+; GCN-NEXT: v_mul_hi_u32 v13, v9, v4
+; GCN-NEXT: v_mul_lo_u32 v14, v9, v4
+; GCN-NEXT: v_add_i32_e32 v11, vcc, v13, v11
+; GCN-NEXT: v_mul_hi_u32 v13, v4, v14
+; GCN-NEXT: v_mul_hi_u32 v15, v8, v14
+; GCN-NEXT: v_mul_lo_u32 v14, v8, v14
+; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12
+; GCN-NEXT: v_mul_hi_u32 v12, v4, v11
+; GCN-NEXT: v_mul_lo_u32 v16, v4, v11
+; GCN-NEXT: v_mul_hi_u32 v17, v8, v11
+; GCN-NEXT: v_mul_lo_u32 v11, v8, v11
+; GCN-NEXT: v_add_i32_e32 v13, vcc, v13, v16
+; GCN-NEXT: v_addc_u32_e32 v12, vcc, v6, v12, vcc
+; GCN-NEXT: v_add_i32_e32 v13, vcc, v14, v13
+; GCN-NEXT: v_addc_u32_e32 v12, vcc, v12, v15, vcc
+; GCN-NEXT: v_addc_u32_e32 v13, vcc, v17, v5, vcc
+; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11
+; GCN-NEXT: v_addc_u32_e32 v12, vcc, v6, v13, vcc
+; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v11
+; GCN-NEXT: v_addc_u32_e64 v11, vcc, v8, v12, s[4:5]
+; GCN-NEXT: v_mul_hi_u32 v13, v9, v4
+; GCN-NEXT: v_mul_lo_u32 v10, v10, v4
+; GCN-NEXT: v_mul_lo_u32 v14, v9, v4
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v12
+; GCN-NEXT: v_mul_lo_u32 v9, v9, v11
+; GCN-NEXT: v_mul_hi_u32 v12, v11, v14
+; GCN-NEXT: v_mul_lo_u32 v15, v11, v14
+; GCN-NEXT: v_mul_hi_u32 v14, v4, v14
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v13, v9
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10
+; GCN-NEXT: v_mul_hi_u32 v10, v11, v9
+; GCN-NEXT: v_mul_hi_u32 v13, v4, v9
+; GCN-NEXT: v_mul_lo_u32 v16, v4, v9
+; GCN-NEXT: v_mul_lo_u32 v9, v11, v9
+; GCN-NEXT: v_add_i32_e32 v11, vcc, v14, v16
+; GCN-NEXT: v_addc_u32_e32 v13, vcc, v6, v13, vcc
+; GCN-NEXT: v_add_i32_e32 v11, vcc, v15, v11
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v13, v12, vcc
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v5, vcc
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v9
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v6, v10, vcc
+; GCN-NEXT: v_addc_u32_e64 v8, vcc, v8, v10, s[4:5]
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v9
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
+; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
+; GCN-NEXT: v_mul_hi_u32 v10, v1, v4
+; GCN-NEXT: v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT: v_mul_hi_u32 v11, v0, v8
+; GCN-NEXT: v_mul_lo_u32 v12, v0, v8
+; GCN-NEXT: v_mul_hi_u32 v13, v1, v8
+; GCN-NEXT: v_mul_lo_u32 v8, v1, v8
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v6, v11, vcc
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v9
+; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v10, vcc
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, v13, v5, vcc
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
+; GCN-NEXT: v_mul_lo_u32 v8, v3, v4
+; GCN-NEXT: v_mul_lo_u32 v4, v2, v4
+; GCN-NEXT: v_mul_lo_u32 v5, v2, v5
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, v1, v5
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
+; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v6, v3, vcc
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
+; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, v0, v2
+; GCN-NEXT: v_subb_u32_e64 v8, s[4:5], v4, v3, vcc
+; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v2
+; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, v6, v2
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3
+; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v3
+; GCN-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; GCN-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v8, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GCN-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v8, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
+; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5]
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v7
+; GCN-NEXT: v_xor_b32_e32 v0, v0, v7
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v7, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = srem i64 %x, %y
+ ret i64 %result
+}
+
+define amdgpu_kernel void @s_test_srem23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_srem23_64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s9, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s3, 0xf000
+; GCN-NEXT: s_mov_b32 s2, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s0, s4
+; GCN-NEXT: s_mov_b32 s1, s5
+; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 41
+; GCN-NEXT: s_ashr_i64 s[6:7], s[8:9], 41
+; GCN-NEXT: s_xor_b32 s5, s4, s6
+; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6
+; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4
+; GCN-NEXT: s_ashr_i32 s5, s5, 30
+; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GCN-NEXT: s_or_b32 s5, s5, 1
+; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
+; GCN-NEXT: v_trunc_f32_e32 v2, v2
+; GCN-NEXT: v_mov_b32_e32 v3, s5
+; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GCN-NEXT: v_cvt_i32_f32_e32 v1, v2
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s6
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 23
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-NEXT: s_endpgm
+ %1 = ashr i64 %x, 41
+ %2 = ashr i64 %y, 41
+ %result = srem i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_srem24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_srem24_64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s9, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s3, 0xf000
+; GCN-NEXT: s_mov_b32 s2, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s0, s4
+; GCN-NEXT: s_mov_b32 s1, s5
+; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 40
+; GCN-NEXT: s_ashr_i64 s[6:7], s[8:9], 40
+; GCN-NEXT: s_xor_b32 s5, s4, s6
+; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6
+; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4
+; GCN-NEXT: s_ashr_i32 s5, s5, 30
+; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GCN-NEXT: s_or_b32 s5, s5, 1
+; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
+; GCN-NEXT: v_trunc_f32_e32 v2, v2
+; GCN-NEXT: v_mov_b32_e32 v3, s5
+; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GCN-NEXT: v_cvt_i32_f32_e32 v1, v2
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s6
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-NEXT: s_endpgm
+ %1 = ashr i64 %x, 40
+ %2 = ashr i64 %y, 40
+ %result = srem i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define i64 @v_test_srem24_64(i64 %x, i64 %y) {
+; GCN-LABEL: v_test_srem24_64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
+; GCN-NEXT: v_ashr_i64 v[1:2], v[2:3], 40
+; GCN-NEXT: v_xor_b32_e32 v2, v0, v1
+; GCN-NEXT: v_cvt_f32_i32_e32 v3, v0
+; GCN-NEXT: v_cvt_f32_i32_e32 v4, v1
+; GCN-NEXT: v_ashrrev_i32_e32 v2, 30, v2
+; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v4
+; GCN-NEXT: v_or_b32_e32 v2, 1, v2
+; GCN-NEXT: v_mul_f32_e32 v5, v3, v5
+; GCN-NEXT: v_trunc_f32_e32 v5, v5
+; GCN-NEXT: v_mad_f32 v3, -v5, v4, v3
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v4|
+; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GCN-NEXT: v_cvt_i32_f32_e32 v3, v5
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT: v_mul_lo_u32 v1, v2, v1
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %1 = ashr i64 %x, 40
+ %2 = ashr i64 %y, 40
+ %result = srem i64 %1, %2
+ ret i64 %result
+}
+
+define amdgpu_kernel void @s_test_srem25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_srem25_64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s3, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s11, 0xf000
+; GCN-NEXT: s_mov_b32 s10, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s8, s4
+; GCN-NEXT: s_mov_b32 s9, s5
+; GCN-NEXT: s_ashr_i64 s[0:1], s[6:7], 39
+; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 39
+; GCN-NEXT: s_ashr_i32 s1, s2, 31
+; GCN-NEXT: s_ashr_i32 s4, s0, 31
+; GCN-NEXT: s_add_i32 s2, s2, s1
+; GCN-NEXT: s_add_i32 s0, s0, s4
+; GCN-NEXT: s_xor_b32 s5, s2, s1
+; GCN-NEXT: s_xor_b32 s2, s0, s4
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s5
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s5
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s2
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s5
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s2, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, s5, v1
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s2, v0
+; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s5, v1
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s5, v1
+; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
+; GCN-NEXT: v_xor_b32_e32 v0, s4, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GCN-NEXT: s_endpgm
+ %1 = ashr i64 %x, 39
+ %2 = ashr i64 %y, 39
+ %result = srem i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_srem31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_srem31_64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s3, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s11, 0xf000
+; GCN-NEXT: s_mov_b32 s10, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s8, s4
+; GCN-NEXT: s_mov_b32 s9, s5
+; GCN-NEXT: s_ashr_i64 s[0:1], s[6:7], 33
+; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 33
+; GCN-NEXT: s_ashr_i32 s1, s2, 31
+; GCN-NEXT: s_ashr_i32 s4, s0, 31
+; GCN-NEXT: s_add_i32 s2, s2, s1
+; GCN-NEXT: s_add_i32 s0, s0, s4
+; GCN-NEXT: s_xor_b32 s5, s2, s1
+; GCN-NEXT: s_xor_b32 s2, s0, s4
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s5
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s5
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s2
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s5
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s2, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, s5, v1
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s2, v0
+; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s5, v1
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s5, v1
+; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
+; GCN-NEXT: v_xor_b32_e32 v0, s4, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GCN-NEXT: s_endpgm
+ %1 = ashr i64 %x, 33
+ %2 = ashr i64 %y, 33
+ %result = srem i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+; 32 known sign bits
+define amdgpu_kernel void @s_test_srem32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_srem32_64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s2, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s11, 0xf000
+; GCN-NEXT: s_mov_b32 s10, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s8, s4
+; GCN-NEXT: s_mov_b32 s9, s5
+; GCN-NEXT: s_ashr_i32 s0, s2, 31
+; GCN-NEXT: s_ashr_i32 s4, s7, 31
+; GCN-NEXT: s_add_i32 s2, s2, s0
+; GCN-NEXT: s_add_i32 s1, s7, s4
+; GCN-NEXT: s_xor_b32 s5, s2, s0
+; GCN-NEXT: s_xor_b32 s2, s1, s4
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s5
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s5
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s2
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s5
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s2, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, s5, v1
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s2, v0
+; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s5, v1
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s5, v1
+; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
+; GCN-NEXT: v_xor_b32_e32 v0, s4, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GCN-NEXT: s_endpgm
+ %1 = ashr i64 %x, 32
+ %2 = ashr i64 %y, 32
+ %result = srem i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+; 33 known sign bits
+define amdgpu_kernel void @s_test_srem33_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_srem33_64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s4, s8
+; GCN-NEXT: s_mov_b32 s5, s9
+; GCN-NEXT: s_ashr_i64 s[0:1], s[10:11], 31
+; GCN-NEXT: s_ashr_i32 s8, s3, 31
+; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 31
+; GCN-NEXT: s_mov_b32 s9, s8
+; GCN-NEXT: s_add_u32 s2, s2, s8
+; GCN-NEXT: s_addc_u32 s3, s3, s8
+; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9]
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3
+; GCN-NEXT: s_sub_u32 s12, 0, s2
+; GCN-NEXT: v_mov_b32_e32 v4, s3
+; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; GCN-NEXT: s_subb_u32 s13, 0, s3
+; GCN-NEXT: s_ashr_i32 s8, s11, 31
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
+; GCN-NEXT: s_mov_b32 s9, s8
+; GCN-NEXT: s_add_u32 s0, s0, s8
+; GCN-NEXT: v_mov_b32_e32 v3, s8
+; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
+; GCN-NEXT: s_addc_u32 s1, s1, s8
+; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2
+; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[8:9]
+; GCN-NEXT: v_trunc_f32_e32 v5, v5
+; GCN-NEXT: v_mov_b32_e32 v6, s11
+; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_lo_u32 v7, s12, v5
+; GCN-NEXT: v_mul_lo_u32 v8, s13, v2
+; GCN-NEXT: v_mul_hi_u32 v9, s12, v2
+; GCN-NEXT: v_mul_lo_u32 v10, s12, v2
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7
+; GCN-NEXT: v_mul_hi_u32 v9, v2, v10
+; GCN-NEXT: v_mul_hi_u32 v11, v5, v10
+; GCN-NEXT: v_mul_lo_u32 v10, v5, v10
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GCN-NEXT: v_mul_hi_u32 v8, v2, v7
+; GCN-NEXT: v_mul_lo_u32 v12, v2, v7
+; GCN-NEXT: v_mul_hi_u32 v13, v5, v7
+; GCN-NEXT: v_mul_lo_u32 v7, v5, v7
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v11, vcc
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v9, vcc
+; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v7
+; GCN-NEXT: v_addc_u32_e64 v7, vcc, v5, v8, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v9, s12, v2
+; GCN-NEXT: v_mul_lo_u32 v10, s13, v2
+; GCN-NEXT: v_mul_lo_u32 v11, s12, v2
+; GCN-NEXT: v_mul_lo_u32 v12, s12, v7
+; GCN-NEXT: v_mul_hi_u32 v13, v7, v11
+; GCN-NEXT: v_mul_lo_u32 v14, v7, v11
+; GCN-NEXT: v_mul_hi_u32 v11, v2, v11
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT: v_mul_hi_u32 v10, v7, v9
+; GCN-NEXT: v_mul_hi_u32 v12, v2, v9
+; GCN-NEXT: v_mul_lo_u32 v15, v2, v9
+; GCN-NEXT: v_mul_lo_u32 v7, v7, v9
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v15
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v1, v12, vcc
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v14, v9
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v13, vcc
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v10, vcc
+; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; GCN-NEXT: v_mul_hi_u32 v7, s10, v2
+; GCN-NEXT: v_mul_hi_u32 v8, s11, v2
+; GCN-NEXT: v_mul_lo_u32 v2, s11, v2
+; GCN-NEXT: v_mul_hi_u32 v9, s10, v5
+; GCN-NEXT: v_mul_lo_u32 v10, s10, v5
+; GCN-NEXT: v_mul_hi_u32 v11, s11, v5
+; GCN-NEXT: v_mul_lo_u32 v5, s11, v5
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v1, v9, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v8, vcc
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v11, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc
+; GCN-NEXT: v_mul_hi_u32 v1, s2, v2
+; GCN-NEXT: v_mul_lo_u32 v5, s3, v2
+; GCN-NEXT: v_mul_lo_u32 v2, s2, v2
+; GCN-NEXT: v_mul_lo_u32 v0, s2, v0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v5
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s11, v0
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, s10, v2
+; GCN-NEXT: v_subb_u32_e64 v1, s[0:1], v1, v4, vcc
+; GCN-NEXT: v_subb_u32_e32 v0, vcc, v6, v0, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
+; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v6, vcc, s2, v2
+; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v1, v4, vcc
+; GCN-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v6
+; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v8, vcc, s2, v6
+; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v0
+; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1]
+; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[0:1]
+; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v0
+; GCN-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
+; GCN-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v1, v6, v8, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[0:1]
+; GCN-NEXT: v_xor_b32_e32 v2, s8, v0
+; GCN-NEXT: v_xor_b32_e32 v0, s8, v1
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v2, v3, vcc
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %1 = ashr i64 %x, 31
+ %2 = ashr i64 %y, 31
+ %result = srem i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_srem24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
+; GCN-LABEL: s_test_srem24_48:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s2, s[0:1], 0xb
+; GCN-NEXT: s_load_dword s3, s[0:1], 0xc
+; GCN-NEXT: s_load_dword s8, s[0:1], 0xd
+; GCN-NEXT: s_load_dword s9, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_sext_i32_i16 s0, s3
+; GCN-NEXT: s_sext_i32_i16 s1, s9
+; GCN-NEXT: v_mov_b32_e32 v0, s8
+; GCN-NEXT: v_mov_b32_e32 v1, s2
+; GCN-NEXT: v_alignbit_b32 v0, s1, v0, 24
+; GCN-NEXT: v_alignbit_b32 v1, s0, v1, 24
+; GCN-NEXT: v_xor_b32_e32 v2, v1, v0
+; GCN-NEXT: v_cvt_f32_i32_e32 v3, v1
+; GCN-NEXT: v_cvt_f32_i32_e32 v4, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v2, 30, v2
+; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v4
+; GCN-NEXT: v_or_b32_e32 v2, 1, v2
+; GCN-NEXT: v_mul_f32_e32 v5, v3, v5
+; GCN-NEXT: v_trunc_f32_e32 v5, v5
+; GCN-NEXT: v_mad_f32 v3, -v5, v4, v3
+; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v4|
+; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT: v_mul_lo_u32 v0, v2, v0
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4
+; GCN-NEXT: s_endpgm
+ %1 = ashr i48 %x, 24
+ %2 = ashr i48 %y, 24
+ %result = srem i48 %1, %2
+ store i48 %result, i48 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_srem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
+; GCN-LABEL: s_test_srem_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_ashr_i32 s8, s3, 31
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: s_mov_b32 s9, s8
+; GCN-NEXT: s_add_u32 s0, s2, s8
+; GCN-NEXT: s_addc_u32 s1, s3, s8
+; GCN-NEXT: s_xor_b64 s[2:3], s[0:1], s[8:9]
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3
+; GCN-NEXT: s_sub_u32 s8, 0, s2
+; GCN-NEXT: v_mov_b32_e32 v4, s3
+; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; GCN-NEXT: s_subb_u32 s9, 0, s3
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
+; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_lo_u32 v5, s8, v3
+; GCN-NEXT: v_mul_lo_u32 v6, s9, v2
+; GCN-NEXT: v_mul_hi_u32 v7, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v8, s8, v2
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GCN-NEXT: v_mul_hi_u32 v7, v2, v8
+; GCN-NEXT: v_mul_hi_u32 v9, v3, v8
+; GCN-NEXT: v_mul_lo_u32 v8, v3, v8
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
+; GCN-NEXT: v_mul_hi_u32 v6, v2, v5
+; GCN-NEXT: v_mul_lo_u32 v10, v2, v5
+; GCN-NEXT: v_mul_hi_u32 v11, v3, v5
+; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v6, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v9, vcc
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v7, vcc
+; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v5
+; GCN-NEXT: v_addc_u32_e64 v5, vcc, v3, v6, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v7, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v8, s9, v2
+; GCN-NEXT: v_mul_lo_u32 v9, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v10, s8, v5
+; GCN-NEXT: v_mul_hi_u32 v11, v5, v9
+; GCN-NEXT: v_mul_lo_u32 v12, v5, v9
+; GCN-NEXT: v_mul_hi_u32 v9, v2, v9
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT: v_mul_hi_u32 v8, v5, v7
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v7
+; GCN-NEXT: v_mul_lo_u32 v13, v2, v7
+; GCN-NEXT: v_mul_lo_u32 v5, v5, v7
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v13
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v1, v10, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v12, v7
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v11, vcc
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v8, vcc
+; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v5, 24, v2
+; GCN-NEXT: v_mul_hi_u32 v2, 0, v2
+; GCN-NEXT: v_mul_hi_u32 v6, 24, v3
+; GCN-NEXT: v_mul_lo_u32 v7, v3, 24
+; GCN-NEXT: v_mul_hi_u32 v3, 0, v3
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v6, vcc
+; GCN-NEXT: v_add_i32_e32 v5, vcc, 0, v5
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GCN-NEXT: v_mul_hi_u32 v2, s2, v1
+; GCN-NEXT: v_mul_lo_u32 v3, s3, v1
+; GCN-NEXT: v_mul_lo_u32 v1, s2, v1
+; GCN-NEXT: v_mul_lo_u32 v0, s2, v0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0, v0
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 24, v1
+; GCN-NEXT: v_subb_u32_e64 v1, s[0:1], v2, v4, vcc
+; GCN-NEXT: v_subb_u32_e32 v0, vcc, 0, v0, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
+; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s2, v3
+; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v1, v4, vcc
+; GCN-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v5
+; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v7, vcc, s2, v5
+; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v0
+; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
+; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1]
+; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v0
+; GCN-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
+; GCN-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
+; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1]
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %result = srem i64 24, %x
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define i64 @v_test_srem_k_num_i64(i64 %x) {
+; GCN-LABEL: v_test_srem_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GCN-NEXT: v_mov_b32_e32 v3, 0
+; GCN-NEXT: v_mov_b32_e32 v4, 0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v2
+; GCN-NEXT: v_xor_b32_e32 v0, v0, v2
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0
+; GCN-NEXT: v_cvt_f32_u32_e32 v5, v1
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v0
+; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v1, vcc
+; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v5
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
+; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2
+; GCN-NEXT: v_trunc_f32_e32 v5, v5
+; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_lo_u32 v8, v6, v5
+; GCN-NEXT: v_mul_lo_u32 v9, v7, v2
+; GCN-NEXT: v_mul_hi_u32 v10, v6, v2
+; GCN-NEXT: v_mul_lo_u32 v11, v6, v2
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v11
+; GCN-NEXT: v_mul_hi_u32 v12, v5, v11
+; GCN-NEXT: v_mul_lo_u32 v11, v5, v11
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9
+; GCN-NEXT: v_mul_hi_u32 v9, v2, v8
+; GCN-NEXT: v_mul_lo_u32 v13, v2, v8
+; GCN-NEXT: v_mul_hi_u32 v14, v5, v8
+; GCN-NEXT: v_mul_lo_u32 v8, v5, v8
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v13
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v4, v9, vcc
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v12, vcc
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v4, v10, vcc
+; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v8
+; GCN-NEXT: v_addc_u32_e64 v8, vcc, v5, v9, s[4:5]
+; GCN-NEXT: v_mul_hi_u32 v10, v6, v2
+; GCN-NEXT: v_mul_lo_u32 v7, v7, v2
+; GCN-NEXT: v_mul_lo_u32 v11, v6, v2
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9
+; GCN-NEXT: v_mul_lo_u32 v6, v6, v8
+; GCN-NEXT: v_mul_hi_u32 v9, v8, v11
+; GCN-NEXT: v_mul_lo_u32 v12, v8, v11
+; GCN-NEXT: v_mul_hi_u32 v11, v2, v11
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GCN-NEXT: v_mul_hi_u32 v7, v8, v6
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v6
+; GCN-NEXT: v_mul_lo_u32 v13, v2, v6
+; GCN-NEXT: v_mul_lo_u32 v6, v8, v6
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v11, v13
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v10, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v12, v8
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v9, vcc
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v4, v7, vcc
+; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, 24, v2
+; GCN-NEXT: v_mul_hi_u32 v2, 0, v2
+; GCN-NEXT: v_mul_hi_u32 v7, 24, v5
+; GCN-NEXT: v_mul_lo_u32 v8, v5, 24
+; GCN-NEXT: v_mul_hi_u32 v5, 0, v5
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
+; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, 0, v6
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
+; GCN-NEXT: v_mul_lo_u32 v5, v1, v2
+; GCN-NEXT: v_mul_lo_u32 v2, v0, v2
+; GCN-NEXT: v_mul_lo_u32 v3, v0, v3
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, 24, v2
+; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
+; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0
+; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, v2, v0
+; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v4, v1, vcc
+; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0
+; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v6, v0
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v1
+; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[4:5]
+; GCN-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v4, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v10, v8, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5]
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = srem i64 24, %x
+ ret i64 %result
+}
+
+define i64 @v_test_srem_pow2_k_num_i64(i64 %x) {
+; GCN-LABEL: v_test_srem_pow2_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GCN-NEXT: v_mov_b32_e32 v3, 0
+; GCN-NEXT: v_mov_b32_e32 v4, 0
+; GCN-NEXT: s_mov_b32 s6, 0x8000
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v2
+; GCN-NEXT: v_xor_b32_e32 v0, v0, v2
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0
+; GCN-NEXT: v_cvt_f32_u32_e32 v5, v1
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v0
+; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v1, vcc
+; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v5
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
+; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2
+; GCN-NEXT: v_trunc_f32_e32 v5, v5
+; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_lo_u32 v8, v6, v5
+; GCN-NEXT: v_mul_lo_u32 v9, v7, v2
+; GCN-NEXT: v_mul_hi_u32 v10, v6, v2
+; GCN-NEXT: v_mul_lo_u32 v11, v6, v2
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v11
+; GCN-NEXT: v_mul_hi_u32 v12, v5, v11
+; GCN-NEXT: v_mul_lo_u32 v11, v5, v11
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9
+; GCN-NEXT: v_mul_hi_u32 v9, v2, v8
+; GCN-NEXT: v_mul_lo_u32 v13, v2, v8
+; GCN-NEXT: v_mul_hi_u32 v14, v5, v8
+; GCN-NEXT: v_mul_lo_u32 v8, v5, v8
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v13
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v4, v9, vcc
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v12, vcc
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v4, v10, vcc
+; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v8
+; GCN-NEXT: v_addc_u32_e64 v8, vcc, v5, v9, s[4:5]
+; GCN-NEXT: v_mul_hi_u32 v10, v6, v2
+; GCN-NEXT: v_mul_lo_u32 v7, v7, v2
+; GCN-NEXT: v_mul_lo_u32 v11, v6, v2
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9
+; GCN-NEXT: v_mul_lo_u32 v6, v6, v8
+; GCN-NEXT: v_mul_hi_u32 v9, v8, v11
+; GCN-NEXT: v_mul_lo_u32 v12, v8, v11
+; GCN-NEXT: v_mul_hi_u32 v11, v2, v11
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GCN-NEXT: v_mul_hi_u32 v7, v8, v6
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v6
+; GCN-NEXT: v_mul_lo_u32 v13, v2, v6
+; GCN-NEXT: v_mul_lo_u32 v6, v8, v6
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v11, v13
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v10, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v12, v8
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v9, vcc
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v4, v7, vcc
+; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, s6, v2
+; GCN-NEXT: v_mul_hi_u32 v2, 0, v2
+; GCN-NEXT: v_mul_hi_u32 v7, s6, v5
+; GCN-NEXT: v_lshlrev_b32_e32 v8, 15, v5
+; GCN-NEXT: v_mul_hi_u32 v5, 0, v5
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
+; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, 0, v6
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
+; GCN-NEXT: v_mul_lo_u32 v5, v1, v2
+; GCN-NEXT: v_mul_lo_u32 v2, v0, v2
+; GCN-NEXT: v_mul_lo_u32 v3, v0, v3
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
+; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
+; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0
+; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, v2, v0
+; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v4, v1, vcc
+; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0
+; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v6, v0
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v1
+; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[4:5]
+; GCN-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v4, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v10, v8, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5]
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = srem i64 32768, %x
+ ret i64 %result
+}
+
+define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
+; GCN-LABEL: v_test_srem_pow2_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v0, v2
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; GCN-NEXT: v_and_b32_e32 v2, 0xffff8000, v2
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = srem i64 %x, 32768
+ ret i64 %result
+}
+
+define amdgpu_kernel void @s_test_srem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
+; GCN-LABEL: s_test_srem24_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s2, 0x41c00000
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: s_ashr_i64 s[0:1], s[2:3], 40
+; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0
+; GCN-NEXT: s_ashr_i32 s1, s0, 30
+; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
+; GCN-NEXT: s_or_b32 s1, s1, 1
+; GCN-NEXT: v_mul_f32_e32 v1, s2, v1
+; GCN-NEXT: v_mov_b32_e32 v2, s1
+; GCN-NEXT: v_trunc_f32_e32 v1, v1
+; GCN-NEXT: v_mad_f32 v3, -v1, v0, s2
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v0|
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s0
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %x.shr = ashr i64 %x, 40
+ %result = srem i64 24, %x.shr
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_srem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
+; GCN-LABEL: s_test_srem24_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s2, 0x46b6fe00
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: s_ashr_i64 s[0:1], s[2:3], 40
+; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0
+; GCN-NEXT: s_ashr_i32 s1, s0, 30
+; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
+; GCN-NEXT: s_or_b32 s1, s1, 1
+; GCN-NEXT: v_trunc_f32_e32 v1, v1
+; GCN-NEXT: v_mov_b32_e32 v2, s1
+; GCN-NEXT: v_mad_f32 v0, -v1, s2, v0
+; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT: s_movk_i32 s1, 0x5b7f
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s1
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %x.shr = ashr i64 %x, 40
+ %result = srem i64 %x.shr, 23423
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define i64 @v_test_srem24_k_num_i64(i64 %x) {
+; GCN-LABEL: v_test_srem24_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
+; GCN-NEXT: s_mov_b32 s4, 0x41c00000
+; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v2, 30, v0
+; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v1
+; GCN-NEXT: v_or_b32_e32 v2, 1, v2
+; GCN-NEXT: v_mul_f32_e32 v3, s4, v3
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mad_f32 v4, -v3, v1, s4
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v1|
+; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GCN-NEXT: v_cvt_i32_f32_e32 v2, v3
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GCN-NEXT: v_mul_lo_u32 v0, v1, v0
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %x.shr = ashr i64 %x, 40
+ %result = srem i64 24, %x.shr
+ ret i64 %result
+}
+
+define i64 @v_test_srem24_pow2_k_num_i64(i64 %x) {
+; GCN-LABEL: v_test_srem24_pow2_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
+; GCN-NEXT: s_mov_b32 s4, 0x47000000
+; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v2, 30, v0
+; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v1
+; GCN-NEXT: v_or_b32_e32 v2, 1, v2
+; GCN-NEXT: v_mul_f32_e32 v3, s4, v3
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mad_f32 v4, -v3, v1, s4
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v1|
+; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GCN-NEXT: v_cvt_i32_f32_e32 v2, v3
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GCN-NEXT: v_mul_lo_u32 v0, v1, v0
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %x.shr = ashr i64 %x, 40
+ %result = srem i64 32768, %x.shr
+ ret i64 %result
+}
+
+define i64 @v_test_srem24_pow2_k_den_i64(i64 %x) {
+; GCN-LABEL: v_test_srem24_pow2_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ashr_i64 v[2:3], v[0:1], 40
+; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v1
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 17, v0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff8000, v0
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v2, v0
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %x.shr = ashr i64 %x, 40
+ %result = srem i64 %x.shr, 32768
+ ret i64 %result
+}
diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll
new file mode 100644
index 000000000000..c4795f1769de
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll
@@ -0,0 +1,1201 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_udiv_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s4, s8
+; GCN-NEXT: s_mov_b32 s5, s9
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3
+; GCN-NEXT: s_sub_u32 s8, 0, s2
+; GCN-NEXT: v_mov_b32_e32 v4, s3
+; GCN-NEXT: v_mov_b32_e32 v5, s11
+; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; GCN-NEXT: s_subb_u32 s9, 0, s3
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
+; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_lo_u32 v6, s8, v3
+; GCN-NEXT: v_mul_lo_u32 v7, s9, v2
+; GCN-NEXT: v_mul_hi_u32 v8, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v9, s8, v2
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT: v_mul_hi_u32 v8, v2, v9
+; GCN-NEXT: v_mul_hi_u32 v10, v3, v9
+; GCN-NEXT: v_mul_lo_u32 v9, v3, v9
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GCN-NEXT: v_mul_hi_u32 v7, v2, v6
+; GCN-NEXT: v_mul_lo_u32 v11, v2, v6
+; GCN-NEXT: v_mul_hi_u32 v12, v3, v6
+; GCN-NEXT: v_mul_lo_u32 v6, v3, v6
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v10, vcc
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc
+; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v6
+; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v8, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v9, s9, v2
+; GCN-NEXT: v_mul_lo_u32 v10, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v11, s8, v6
+; GCN-NEXT: v_mul_hi_u32 v12, v6, v10
+; GCN-NEXT: v_mul_lo_u32 v13, v6, v10
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v10
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_mul_hi_u32 v9, v6, v8
+; GCN-NEXT: v_mul_hi_u32 v11, v2, v8
+; GCN-NEXT: v_mul_lo_u32 v14, v2, v8
+; GCN-NEXT: v_mul_lo_u32 v6, v6, v8
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v14
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v1, v11, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v13, v8
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v12, vcc
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v9, vcc
+; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v7, s[0:1]
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, s10, v2
+; GCN-NEXT: v_mul_hi_u32 v7, s11, v2
+; GCN-NEXT: v_mul_lo_u32 v2, s11, v2
+; GCN-NEXT: v_mul_hi_u32 v8, s10, v3
+; GCN-NEXT: v_mul_lo_u32 v9, s10, v3
+; GCN-NEXT: v_mul_hi_u32 v10, s11, v3
+; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v9
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, v8, v7, vcc
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v10, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc
+; GCN-NEXT: v_mul_hi_u32 v1, s2, v2
+; GCN-NEXT: v_mul_lo_u32 v3, s3, v2
+; GCN-NEXT: v_mul_lo_u32 v6, s2, v2
+; GCN-NEXT: v_mul_lo_u32 v7, s2, v0
+; GCN-NEXT: v_add_i32_e32 v8, vcc, 2, v2
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v10, vcc, 1, v2
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v7
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, s11, v1
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, s10, v6
+; GCN-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
+; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s2, v6
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v5, v1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v6
+; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GCN-NEXT: v_subbrev_u32_e64 v3, vcc, 0, v3, s[0:1]
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v4
+; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
+; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v3, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v10, v8, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %result = udiv i64 %x, %y
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define i64 @v_test_udiv_i64(i64 %x, i64 %y) {
+; GCN-LABEL: v_test_udiv_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2
+; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
+; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc
+; GCN-NEXT: v_mov_b32_e32 v8, 0
+; GCN-NEXT: v_mov_b32_e32 v9, 0
+; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
+; GCN-NEXT: v_rcp_f32_e32 v4, v4
+; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
+; GCN-NEXT: v_trunc_f32_e32 v5, v5
+; GCN-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GCN-NEXT: v_mul_lo_u32 v10, v6, v5
+; GCN-NEXT: v_mul_lo_u32 v11, v7, v4
+; GCN-NEXT: v_mul_hi_u32 v12, v6, v4
+; GCN-NEXT: v_mul_lo_u32 v13, v6, v4
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v12, v10
+; GCN-NEXT: v_mul_hi_u32 v12, v4, v13
+; GCN-NEXT: v_mul_hi_u32 v14, v5, v13
+; GCN-NEXT: v_mul_lo_u32 v13, v5, v13
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v11
+; GCN-NEXT: v_mul_hi_u32 v11, v4, v10
+; GCN-NEXT: v_mul_lo_u32 v15, v4, v10
+; GCN-NEXT: v_mul_hi_u32 v16, v5, v10
+; GCN-NEXT: v_mul_lo_u32 v10, v5, v10
+; GCN-NEXT: v_add_i32_e32 v12, vcc, v12, v15
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v9, v11, vcc
+; GCN-NEXT: v_add_i32_e32 v12, vcc, v13, v12
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v11, v14, vcc
+; GCN-NEXT: v_addc_u32_e32 v12, vcc, v16, v8, vcc
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v9, v12, vcc
+; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v10
+; GCN-NEXT: v_addc_u32_e64 v10, vcc, v5, v11, s[4:5]
+; GCN-NEXT: v_mul_hi_u32 v12, v6, v4
+; GCN-NEXT: v_mul_lo_u32 v7, v7, v4
+; GCN-NEXT: v_mul_lo_u32 v13, v6, v4
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v11
+; GCN-NEXT: v_mul_lo_u32 v6, v6, v10
+; GCN-NEXT: v_mul_hi_u32 v11, v10, v13
+; GCN-NEXT: v_mul_lo_u32 v14, v10, v13
+; GCN-NEXT: v_mul_hi_u32 v13, v4, v13
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v12, v6
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GCN-NEXT: v_mul_hi_u32 v7, v10, v6
+; GCN-NEXT: v_mul_hi_u32 v12, v4, v6
+; GCN-NEXT: v_mul_lo_u32 v15, v4, v6
+; GCN-NEXT: v_mul_lo_u32 v6, v10, v6
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v13, v15
+; GCN-NEXT: v_addc_u32_e32 v12, vcc, v9, v12, vcc
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v14, v10
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v12, v11, vcc
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc
+; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, v0, v4
+; GCN-NEXT: v_mul_hi_u32 v7, v1, v4
+; GCN-NEXT: v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT: v_mul_hi_u32 v10, v0, v5
+; GCN-NEXT: v_mul_lo_u32 v11, v0, v5
+; GCN-NEXT: v_mul_hi_u32 v12, v1, v5
+; GCN-NEXT: v_mul_lo_u32 v5, v1, v5
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v11
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v9, v10, vcc
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
+; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v7, vcc
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v12, v8, vcc
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
+; GCN-NEXT: v_mul_lo_u32 v7, v3, v4
+; GCN-NEXT: v_mul_lo_u32 v8, v2, v4
+; GCN-NEXT: v_mul_lo_u32 v9, v2, v5
+; GCN-NEXT: v_add_i32_e32 v10, vcc, 2, v4
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc
+; GCN-NEXT: v_add_i32_e32 v12, vcc, 1, v4
+; GCN-NEXT: v_addc_u32_e32 v13, vcc, 0, v5, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v9
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GCN-NEXT: v_sub_i32_e32 v7, vcc, v1, v6
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
+; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v7, v3, vcc
+; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v2
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
+; GCN-NEXT: v_subbrev_u32_e64 v6, vcc, 0, v7, s[4:5]
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v8, v2
+; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
+; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v3
+; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v6, v3
+; GCN-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v12, v10, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v4, v1, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v1, v13, v11, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[4:5]
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = udiv i64 %x, %y
+ ret i64 %result
+}
+
+define amdgpu_kernel void @s_test_udiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_udiv24_64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s2, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s11, 0xf000
+; GCN-NEXT: s_mov_b32 s10, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s8, s4
+; GCN-NEXT: s_mov_b32 s9, s5
+; GCN-NEXT: s_lshr_b32 s3, s7, 8
+; GCN-NEXT: s_lshr_b32 s2, s2, 8
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s2
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s2
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s3
+; GCN-NEXT: v_mul_lo_u32 v1, v0, s2
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s3, v1
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s3, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
+; GCN-NEXT: s_and_b64 vcc, vcc, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1]
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GCN-NEXT: s_endpgm
+ %1 = lshr i64 %x, 40
+ %2 = lshr i64 %y, 40
+ %result = udiv i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define i64 @v_test_udiv24_i64(i64 %x, i64 %y) {
+; GCN-LABEL: v_test_udiv24_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
+; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, v1
+; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_hi_u32 v3, v2, v1
+; GCN-NEXT: v_mul_lo_u32 v4, v2, v1
+; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v4
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GCN-NEXT: v_mul_hi_u32 v3, v3, v2
+; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v2, v3
+; GCN-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v3
+; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GCN-NEXT: v_mul_hi_u32 v2, v2, v0
+; GCN-NEXT: v_mul_lo_u32 v3, v2, v1
+; GCN-NEXT: v_add_i32_e32 v4, vcc, 1, v2
+; GCN-NEXT: v_add_i32_e32 v5, vcc, -1, v2
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
+; GCN-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v3
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v1
+; GCN-NEXT: s_and_b64 s[4:5], s[4:5], vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %1 = lshr i64 %x, 40
+ %2 = lshr i64 %y, 40
+ %result = udiv i64 %1, %2
+ ret i64 %result
+}
+
+define amdgpu_kernel void @s_test_udiv32_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_udiv32_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s2, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s11, 0xf000
+; GCN-NEXT: s_mov_b32 s10, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s8, s4
+; GCN-NEXT: s_mov_b32 s9, s5
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s2
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s2
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s7
+; GCN-NEXT: v_mul_lo_u32 v1, v0, s2
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s7, v1
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s7, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
+; GCN-NEXT: s_and_b64 vcc, vcc, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1]
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GCN-NEXT: s_endpgm
+ %1 = lshr i64 %x, 32
+ %2 = lshr i64 %y, 32
+ %result = udiv i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_udiv31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_udiv31_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s2, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s11, 0xf000
+; GCN-NEXT: s_mov_b32 s10, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s8, s4
+; GCN-NEXT: s_mov_b32 s9, s5
+; GCN-NEXT: s_lshr_b32 s3, s7, 1
+; GCN-NEXT: s_lshr_b32 s2, s2, 1
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s2
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s2
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s3
+; GCN-NEXT: v_mul_lo_u32 v1, v0, s2
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s3, v1
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s3, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
+; GCN-NEXT: s_and_b64 vcc, vcc, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1]
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GCN-NEXT: s_endpgm
+ %1 = lshr i64 %x, 33
+ %2 = lshr i64 %y, 33
+ %result = udiv i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_udiv23_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_udiv23_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s8, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s3, 0xf000
+; GCN-NEXT: s_mov_b32 s2, -1
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s0, s4
+; GCN-NEXT: s_mov_b32 s1, s5
+; GCN-NEXT: s_lshr_b32 s4, s7, 9
+; GCN-NEXT: s_lshr_b32 s5, s8, 9
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s4
+; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GCN-NEXT: v_mul_f32_e32 v3, v2, v3
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mad_f32 v2, -v3, v0, v2
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v0|
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GCN-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-NEXT: s_endpgm
+ %1 = lshr i64 %x, 41
+ %2 = lshr i64 %y, 41
+ %result = udiv i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
+; GCN-LABEL: s_test_udiv24_i48:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s2, s[0:1], 0xb
+; GCN-NEXT: s_load_dword s3, s[0:1], 0xc
+; GCN-NEXT: s_load_dword s8, s[0:1], 0xd
+; GCN-NEXT: s_load_dword s9, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: s_mov_b32 s0, 0xffff
+; GCN-NEXT: s_mov_b32 s10, 0xff000000
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_and_b32 s11, s3, s0
+; GCN-NEXT: s_and_b32 s12, s2, s10
+; GCN-NEXT: s_and_b32 s1, s9, s0
+; GCN-NEXT: s_and_b32 s0, s8, s10
+; GCN-NEXT: s_lshr_b64 s[2:3], s[0:1], 24
+; GCN-NEXT: v_mov_b32_e32 v2, s0
+; GCN-NEXT: v_alignbit_b32 v2, s1, v2, 24
+; GCN-NEXT: v_cvt_f32_ubyte3_e32 v3, s1
+; GCN-NEXT: v_mov_b32_e32 v4, s12
+; GCN-NEXT: v_alignbit_b32 v4, s11, v4, 24
+; GCN-NEXT: v_cvt_f32_u32_e32 v5, v2
+; GCN-NEXT: s_sub_u32 s2, 0, s2
+; GCN-NEXT: v_mac_f32_e32 v5, 0x4f800000, v3
+; GCN-NEXT: s_subb_u32 s3, 0, s3
+; GCN-NEXT: v_rcp_f32_e32 v3, v5
+; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3
+; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v3
+; GCN-NEXT: v_trunc_f32_e32 v5, v5
+; GCN-NEXT: v_mac_f32_e32 v3, 0xcf800000, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_mul_lo_u32 v6, s2, v5
+; GCN-NEXT: v_mul_lo_u32 v7, s3, v3
+; GCN-NEXT: v_mul_hi_u32 v8, s2, v3
+; GCN-NEXT: v_mul_lo_u32 v9, s2, v3
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT: v_mul_hi_u32 v8, v3, v9
+; GCN-NEXT: v_mul_hi_u32 v10, v5, v9
+; GCN-NEXT: v_mul_lo_u32 v9, v5, v9
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GCN-NEXT: v_mul_hi_u32 v7, v3, v6
+; GCN-NEXT: v_mul_lo_u32 v11, v3, v6
+; GCN-NEXT: v_mul_hi_u32 v12, v5, v6
+; GCN-NEXT: v_mul_lo_u32 v6, v5, v6
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v10, vcc
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc
+; GCN-NEXT: v_add_i32_e64 v3, s[0:1], v3, v6
+; GCN-NEXT: v_addc_u32_e64 v6, vcc, v5, v7, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v8, s2, v3
+; GCN-NEXT: v_mul_lo_u32 v9, s3, v3
+; GCN-NEXT: v_mul_lo_u32 v10, s2, v3
+; GCN-NEXT: v_mul_lo_u32 v11, s2, v6
+; GCN-NEXT: v_mul_hi_u32 v12, v6, v10
+; GCN-NEXT: v_mul_lo_u32 v13, v6, v10
+; GCN-NEXT: v_mul_hi_u32 v10, v3, v10
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_mul_hi_u32 v9, v6, v8
+; GCN-NEXT: v_mul_hi_u32 v11, v3, v8
+; GCN-NEXT: v_mul_lo_u32 v14, v3, v8
+; GCN-NEXT: v_mul_lo_u32 v6, v6, v8
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v14
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v1, v11, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v13, v8
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v12, vcc
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v9, vcc
+; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[0:1]
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, v4, v3
+; GCN-NEXT: v_mul_hi_u32 v3, 0, v3
+; GCN-NEXT: v_mul_hi_u32 v7, v4, v5
+; GCN-NEXT: v_mul_lo_u32 v8, v4, v5
+; GCN-NEXT: v_mul_hi_u32 v5, 0, v5
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, 0, v6
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v3, vcc
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v3, vcc, 0, v3
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc
+; GCN-NEXT: v_mul_hi_u32 v1, v2, v3
+; GCN-NEXT: v_mul_lo_u32 v5, v2, v3
+; GCN-NEXT: v_mul_lo_u32 v6, v2, v0
+; GCN-NEXT: v_add_i32_e32 v7, vcc, 2, v3
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v9, vcc, 1, v3
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v6
+; GCN-NEXT: v_sub_i32_e32 v4, vcc, v4, v5
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT: v_sub_i32_e32 v5, vcc, v4, v2
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v4, v2
+; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
+; GCN-NEXT: v_subbrev_u32_e32 v6, vcc, 0, v1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v2
+; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, -1, v4, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
+; GCN-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GCN-NEXT: v_cndmask_b32_e32 v2, v9, v7, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v2, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v2, v10, v8, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:4
+; GCN-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %1 = lshr i48 %x, 24
+ %2 = lshr i48 %y, 24
+ %result = udiv i48 %1, %2
+ store i48 %result, i48 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_udiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
+; GCN-LABEL: s_test_udiv_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3
+; GCN-NEXT: s_sub_u32 s8, 0, s2
+; GCN-NEXT: v_mov_b32_e32 v4, s3
+; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; GCN-NEXT: s_subb_u32 s9, 0, s3
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
+; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_lo_u32 v5, s8, v3
+; GCN-NEXT: v_mul_lo_u32 v6, s9, v2
+; GCN-NEXT: v_mul_hi_u32 v7, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v8, s8, v2
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GCN-NEXT: v_mul_hi_u32 v7, v2, v8
+; GCN-NEXT: v_mul_hi_u32 v9, v3, v8
+; GCN-NEXT: v_mul_lo_u32 v8, v3, v8
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
+; GCN-NEXT: v_mul_hi_u32 v6, v2, v5
+; GCN-NEXT: v_mul_lo_u32 v10, v2, v5
+; GCN-NEXT: v_mul_hi_u32 v11, v3, v5
+; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v6, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v9, vcc
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v7, vcc
+; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v5
+; GCN-NEXT: v_addc_u32_e64 v5, vcc, v3, v6, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v7, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v8, s9, v2
+; GCN-NEXT: v_mul_lo_u32 v9, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v10, s8, v5
+; GCN-NEXT: v_mul_hi_u32 v11, v5, v9
+; GCN-NEXT: v_mul_lo_u32 v12, v5, v9
+; GCN-NEXT: v_mul_hi_u32 v9, v2, v9
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT: v_mul_hi_u32 v8, v5, v7
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v7
+; GCN-NEXT: v_mul_lo_u32 v13, v2, v7
+; GCN-NEXT: v_mul_lo_u32 v5, v5, v7
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v13
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v1, v10, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v12, v7
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v11, vcc
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v8, vcc
+; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v2, v2, 24
+; GCN-NEXT: v_mul_hi_u32 v5, v3, 24
+; GCN-NEXT: v_mul_lo_u32 v3, v3, 24
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, v1, v5, vcc
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
+; GCN-NEXT: v_mul_hi_u32 v1, s2, v2
+; GCN-NEXT: v_mul_lo_u32 v3, s3, v2
+; GCN-NEXT: v_mul_lo_u32 v5, s2, v2
+; GCN-NEXT: v_mul_lo_u32 v6, s2, v0
+; GCN-NEXT: v_add_i32_e32 v7, vcc, 2, v2
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v9, vcc, 1, v2
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v6
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
+; GCN-NEXT: v_sub_i32_e32 v5, vcc, 24, v5
+; GCN-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
+; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s2, v5
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v5
+; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GCN-NEXT: v_subbrev_u32_e64 v3, vcc, 0, v3, s[0:1]
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v4
+; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
+; GCN-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v10, v8, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v3, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v9, v7, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %result = udiv i64 24, %x
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+; define i64 @v_test_udiv_k_num_i64(i64 %x) {
+; %result = udiv i64 24, %x
+; ret i64 %result
+; }
+
+define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) {
+; GCN-LABEL: v_test_udiv_pow2_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1
+; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v0
+; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc
+; GCN-NEXT: v_mov_b32_e32 v6, 0
+; GCN-NEXT: v_mov_b32_e32 v7, 0
+; GCN-NEXT: s_mov_b32 s6, 0x8000
+; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
+; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_lo_u32 v8, v4, v3
+; GCN-NEXT: v_mul_lo_u32 v9, v5, v2
+; GCN-NEXT: v_mul_hi_u32 v10, v4, v2
+; GCN-NEXT: v_mul_lo_u32 v11, v4, v2
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v11
+; GCN-NEXT: v_mul_hi_u32 v12, v3, v11
+; GCN-NEXT: v_mul_lo_u32 v11, v3, v11
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9
+; GCN-NEXT: v_mul_hi_u32 v9, v2, v8
+; GCN-NEXT: v_mul_lo_u32 v13, v2, v8
+; GCN-NEXT: v_mul_hi_u32 v14, v3, v8
+; GCN-NEXT: v_mul_lo_u32 v8, v3, v8
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v13
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v9, vcc
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v12, vcc
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v6, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc
+; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v8
+; GCN-NEXT: v_addc_u32_e64 v8, vcc, v3, v9, s[4:5]
+; GCN-NEXT: v_mul_hi_u32 v10, v4, v2
+; GCN-NEXT: v_mul_lo_u32 v5, v5, v2
+; GCN-NEXT: v_mul_lo_u32 v11, v4, v2
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v9
+; GCN-NEXT: v_mul_lo_u32 v4, v4, v8
+; GCN-NEXT: v_mul_hi_u32 v9, v8, v11
+; GCN-NEXT: v_mul_lo_u32 v12, v8, v11
+; GCN-NEXT: v_mul_hi_u32 v11, v2, v11
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v10, v4
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
+; GCN-NEXT: v_mul_hi_u32 v5, v8, v4
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT: v_mul_lo_u32 v13, v2, v4
+; GCN-NEXT: v_mul_lo_u32 v4, v8, v4
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v11, v13
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v7, v10, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v12, v8
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v9, vcc
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc
+; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2
+; GCN-NEXT: v_mul_lo_u32 v3, v1, v2
+; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
+; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
+; GCN-NEXT: v_add_i32_e32 v6, vcc, 2, v2
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v9, vcc, 1, v2
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GCN-NEXT: v_sub_i32_e32 v4, vcc, s6, v5
+; GCN-NEXT: v_sub_i32_e64 v5, s[4:5], 0, v3
+; GCN-NEXT: v_sub_i32_e64 v10, s[4:5], v4, v0
+; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v4, v0
+; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[6:7]
+; GCN-NEXT: v_subb_u32_e64 v5, s[6:7], v5, v1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v10, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[6:7]
+; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_subbrev_u32_e64 v5, vcc, 0, v5, s[4:5]
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
+; GCN-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v3, v1
+; GCN-NEXT: v_cndmask_b32_e32 v3, v10, v4, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v9, v6, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v3
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = udiv i64 32768, %x
+ ret i64 %result
+}
+
+define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) {
+; GCN-LABEL: v_test_udiv_pow2_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 15
+; GCN-NEXT: v_lshrrev_b32_e32 v1, 15, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = udiv i64 %x, 32768
+ ret i64 %result
+}
+
+define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
+; GCN-LABEL: s_test_udiv_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000
+; GCN-NEXT: s_movk_i32 s8, 0xffe8
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: v_mov_b32_e32 v2, 0
+; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000
+; GCN-NEXT: v_rcp_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
+; GCN-NEXT: v_mov_b32_e32 v4, s3
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_lo_u32 v5, v3, s8
+; GCN-NEXT: v_mul_hi_u32 v6, v0, s8
+; GCN-NEXT: v_mul_lo_u32 v7, v0, s8
+; GCN-NEXT: v_subrev_i32_e32 v6, vcc, v0, v6
+; GCN-NEXT: v_mul_hi_u32 v8, v0, v7
+; GCN-NEXT: v_mul_hi_u32 v9, v3, v7
+; GCN-NEXT: v_mul_lo_u32 v7, v3, v7
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
+; GCN-NEXT: v_mul_hi_u32 v6, v0, v5
+; GCN-NEXT: v_mul_lo_u32 v10, v0, v5
+; GCN-NEXT: v_mul_hi_u32 v11, v3, v5
+; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v9, vcc
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v1, vcc
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v7, vcc
+; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v5
+; GCN-NEXT: v_addc_u32_e64 v5, vcc, v3, v6, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v7, v0, s8
+; GCN-NEXT: v_mul_lo_u32 v8, v0, s8
+; GCN-NEXT: v_mul_lo_u32 v9, v5, s8
+; GCN-NEXT: v_subrev_i32_e32 v7, vcc, v0, v7
+; GCN-NEXT: v_mul_hi_u32 v10, v0, v8
+; GCN-NEXT: v_mul_hi_u32 v11, v5, v8
+; GCN-NEXT: v_mul_lo_u32 v8, v5, v8
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT: v_mul_hi_u32 v9, v0, v7
+; GCN-NEXT: v_mul_lo_u32 v12, v0, v7
+; GCN-NEXT: v_mul_hi_u32 v13, v5, v7
+; GCN-NEXT: v_mul_lo_u32 v5, v5, v7
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v12
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v9, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v11, vcc
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v1, vcc
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v8, vcc
+; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v5
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v5, s2, v0
+; GCN-NEXT: v_mul_hi_u32 v6, s3, v0
+; GCN-NEXT: v_mul_lo_u32 v0, s3, v0
+; GCN-NEXT: v_mul_hi_u32 v7, s2, v3
+; GCN-NEXT: v_mul_lo_u32 v8, s2, v3
+; GCN-NEXT: v_mul_hi_u32 v9, s3, v3
+; GCN-NEXT: v_mul_lo_u32 v3, s3, v3
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v5
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v7, v6, vcc
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v9, v1, vcc
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; GCN-NEXT: v_mul_hi_u32 v2, v0, 24
+; GCN-NEXT: v_mul_lo_u32 v3, v0, 24
+; GCN-NEXT: v_mul_lo_u32 v5, v1, 24
+; GCN-NEXT: v_add_i32_e32 v6, vcc, 2, v0
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, 1, v0
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, s2, v3
+; GCN-NEXT: v_subb_u32_e32 v2, vcc, v4, v2, vcc
+; GCN-NEXT: v_subrev_i32_e32 v4, vcc, 24, v3
+; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v3
+; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[0:1]
+; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
+; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v4
+; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GCN-NEXT: v_cndmask_b32_e32 v2, -1, v3, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
+; GCN-NEXT: v_cndmask_b32_e32 v3, -1, v4, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v9, v7, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
+; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v2, v8, v6, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %result = udiv i64 %x, 24
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define i64 @v_test_udiv_k_den_i64(i64 %x) {
+; GCN-LABEL: v_test_udiv_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000
+; GCN-NEXT: s_movk_i32 s6, 0xffe8
+; GCN-NEXT: v_mov_b32_e32 v3, 0
+; GCN-NEXT: v_mov_b32_e32 v4, 0
+; GCN-NEXT: v_madak_f32 v2, 0, v2, 0x41c00000
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
+; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2
+; GCN-NEXT: v_trunc_f32_e32 v5, v5
+; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_lo_u32 v6, v5, s6
+; GCN-NEXT: v_mul_hi_u32 v7, v2, s6
+; GCN-NEXT: v_mul_lo_u32 v8, v2, s6
+; GCN-NEXT: v_subrev_i32_e32 v7, vcc, v2, v7
+; GCN-NEXT: v_mul_hi_u32 v9, v2, v8
+; GCN-NEXT: v_mul_hi_u32 v10, v5, v8
+; GCN-NEXT: v_mul_lo_u32 v8, v5, v8
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GCN-NEXT: v_mul_hi_u32 v7, v2, v6
+; GCN-NEXT: v_mul_lo_u32 v11, v2, v6
+; GCN-NEXT: v_mul_hi_u32 v12, v5, v6
+; GCN-NEXT: v_mul_lo_u32 v6, v5, v6
+; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v11
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v4, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v10, vcc
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v4, v8, vcc
+; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v6
+; GCN-NEXT: v_addc_u32_e64 v6, vcc, v5, v7, s[4:5]
+; GCN-NEXT: v_mul_hi_u32 v8, v2, s6
+; GCN-NEXT: v_mul_lo_u32 v9, v2, s6
+; GCN-NEXT: v_mul_lo_u32 v10, v6, s6
+; GCN-NEXT: v_subrev_i32_e32 v8, vcc, v2, v8
+; GCN-NEXT: v_mul_hi_u32 v11, v2, v9
+; GCN-NEXT: v_mul_hi_u32 v12, v6, v9
+; GCN-NEXT: v_mul_lo_u32 v9, v6, v9
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v8
+; GCN-NEXT: v_mul_lo_u32 v13, v2, v8
+; GCN-NEXT: v_mul_hi_u32 v14, v6, v8
+; GCN-NEXT: v_mul_lo_u32 v6, v6, v8
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v11, v13
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v10, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v12, vcc
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v4, v9, vcc
+; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
+; GCN-NEXT: v_mul_hi_u32 v7, v1, v2
+; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT: v_mul_hi_u32 v8, v0, v5
+; GCN-NEXT: v_mul_lo_u32 v9, v0, v5
+; GCN-NEXT: v_mul_hi_u32 v10, v1, v5
+; GCN-NEXT: v_mul_lo_u32 v5, v1, v5
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v9
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v4, v8, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, v8, v7, vcc
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, v10, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v4, v2, 24
+; GCN-NEXT: v_mul_lo_u32 v5, v2, 24
+; GCN-NEXT: v_mul_lo_u32 v6, v3, 24
+; GCN-NEXT: v_add_i32_e32 v7, vcc, 2, v2
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v9, vcc, 1, v2
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
+; GCN-NEXT: v_subrev_i32_e32 v4, vcc, 24, v0
+; GCN-NEXT: v_cmp_lt_u32_e64 s[4:5], 23, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]
+; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v1, vcc
+; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v4
+; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
+; GCN-NEXT: v_cndmask_b32_e32 v1, -1, v4, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v9, v7, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v1, v10, v8, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5]
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = udiv i64 %x, 24
+ ret i64 %result
+}
+
+define amdgpu_kernel void @s_test_udiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
+; GCN-LABEL: s_test_udiv24_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: s_lshr_b32 s2, s3, 8
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s2
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s2
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, 24
+; GCN-NEXT: v_mul_lo_u32 v1, v0, s2
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0
+; GCN-NEXT: v_cmp_gt_u32_e64 s[0:1], 25, v1
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, 24, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
+; GCN-NEXT: s_and_b64 vcc, vcc, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1]
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %x.shr = lshr i64 %x, 40
+ %result = udiv i64 24, %x.shr
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_udiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
+; GCN-LABEL: s_test_udiv24_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_movk_i32 s2, 0x5b7f
+; GCN-NEXT: s_movk_i32 s8, 0x5b7e
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: s_lshr_b32 s3, s3, 8
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s2
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s2
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s3
+; GCN-NEXT: v_mul_lo_u32 v1, v0, s2
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s3, v1
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s3, v1
+; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s8, v1
+; GCN-NEXT: s_and_b64 vcc, vcc, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1]
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %x.shr = lshr i64 %x, 40
+ %result = udiv i64 %x.shr, 23423
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define i64 @v_test_udiv24_k_num_i64(i64 %x) {
+; GCN-LABEL: v_test_udiv24_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
+; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
+; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GCN-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GCN-NEXT: v_mul_hi_u32 v2, v1, v0
+; GCN-NEXT: v_mul_lo_u32 v3, v1, v0
+; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GCN-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; GCN-NEXT: v_mul_hi_u32 v2, v2, v1
+; GCN-NEXT: v_add_i32_e64 v3, s[4:5], v1, v2
+; GCN-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v1, v1, 24
+; GCN-NEXT: v_mul_lo_u32 v2, v1, v0
+; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v1
+; GCN-NEXT: v_add_i32_e32 v4, vcc, -1, v1
+; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 25, v2
+; GCN-NEXT: v_sub_i32_e64 v2, s[4:5], 24, v2
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v0
+; GCN-NEXT: s_and_b64 s[4:5], s[4:5], vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, v3, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %x.shr = lshr i64 %x, 40
+ %result = udiv i64 24, %x.shr
+ ret i64 %result
+}
+
+define i64 @v_test_udiv24_pow2_k_num_i64(i64 %x) {
+; GCN-LABEL: v_test_udiv24_pow2_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
+; GCN-NEXT: s_mov_b32 s6, 0x8001
+; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
+; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GCN-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GCN-NEXT: v_mul_hi_u32 v2, v1, v0
+; GCN-NEXT: v_mul_lo_u32 v3, v1, v0
+; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GCN-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; GCN-NEXT: v_mul_hi_u32 v2, v2, v1
+; GCN-NEXT: v_add_i32_e64 v3, s[4:5], v1, v2
+; GCN-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v1, 17, v1
+; GCN-NEXT: v_mul_u32_u24_e32 v2, v1, v0
+; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v1
+; GCN-NEXT: v_add_i32_e32 v4, vcc, -1, v1
+; GCN-NEXT: v_cmp_gt_u32_e64 s[4:5], s6, v2
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0x8000, v2
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0
+; GCN-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[4:5]
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %x.shr = lshr i64 %x, 40
+ %result = udiv i64 32768, %x.shr
+ ret i64 %result
+}
+
+define i64 @v_test_udiv24_pow2_k_den_i64(i64 %x) {
+; GCN-LABEL: v_test_udiv24_pow2_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 23, v1
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %x.shr = lshr i64 %x, 40
+ %result = udiv i64 %x.shr, 32768
+ ret i64 %result
+}
diff --git a/llvm/test/CodeGen/AMDGPU/udivrem64.ll b/llvm/test/CodeGen/AMDGPU/udivrem64.r600.ll
similarity index 58%
rename from llvm/test/CodeGen/AMDGPU/udivrem64.ll
rename to llvm/test/CodeGen/AMDGPU/udivrem64.r600.ll
index 32a758b7c7d8..62cab48c65e9 100644
--- a/llvm/test/CodeGen/AMDGPU/udivrem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/udivrem64.r600.ll
@@ -1,9 +1,6 @@
-;RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s
-;RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC %s
-;RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC %s
-;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
+;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s
-;FUNC-LABEL: {{^}}test_udiv:
+;EG-LABEL: {{^}}test_udiv:
;EG: RECIP_UINT
;EG: LSHL {{.*}}, 1,
;EG: BFE_UINT
@@ -36,21 +33,13 @@
;EG: BFE_UINT
;EG: BFE_UINT
;EG: BFE_UINT
-
-;GCN: v_mac_f32_e32 v{{[0-9]+}}, 0x4f800000,
-;GCN: v_rcp_f32_e32
-;GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x5f7ffffc
-;GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x2f800000
-;GCN: v_trunc_f32_e32
-;GCN: v_mac_f32_e32 v{{[0-9]+}}, 0xcf800000
-;GCN: s_endpgm
define amdgpu_kernel void @test_udiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
%result = udiv i64 %x, %y
store i64 %result, i64 addrspace(1)* %out
ret void
}
-;FUNC-LABEL: {{^}}test_urem:
+;EG-LABEL: {{^}}test_urem:
;EG: RECIP_UINT
;EG: BFE_UINT
;EG: BFE_UINT
@@ -83,29 +72,15 @@ define amdgpu_kernel void @test_udiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
;EG: BFE_UINT
;EG: BFE_UINT
;EG: AND_INT {{.*}}, 1,
-
-;GCN: v_mac_f32_e32 v{{[0-9]+}}, 0x4f800000,
-;GCN: v_rcp_f32_e32
-;GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x5f7ffffc
-;GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x2f800000
-;GCN: v_trunc_f32_e32
-;GCN: v_mac_f32_e32 v{{[0-9]+}}, 0xcf800000
-;GCN: s_endpgm
define amdgpu_kernel void @test_urem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
%result = urem i64 %x, %y
store i64 %result, i64 addrspace(1)* %out
ret void
}
-;FUNC-LABEL: {{^}}test_udiv3264:
+;EG-LABEL: {{^}}test_udiv3264:
;EG: RECIP_UINT
;EG-NOT: BFE_UINT
-
-;GCN-NOT: s_bfe_u32
-;GCN-NOT: v_mad_f32
-;SI-NOT: v_lshr_b64
-;VI-NOT: v_lshrrev_b64
-;GCN: s_endpgm
define amdgpu_kernel void @test_udiv3264(i64 addrspace(1)* %out, i64 %x, i64 %y) {
%1 = lshr i64 %x, 33
%2 = lshr i64 %y, 33
@@ -114,15 +89,9 @@ define amdgpu_kernel void @test_udiv3264(i64 addrspace(1)* %out, i64 %x, i64 %y)
ret void
}
-;FUNC-LABEL: {{^}}test_urem3264:
+;EG-LABEL: {{^}}test_urem3264:
;EG: RECIP_UINT
;EG-NOT: BFE_UINT
-
-;GCN-NOT: s_bfe_u32
-;GCN-NOT: v_mad_f32
-;SI-NOT: v_lshr_b64
-;VI-NOT: v_lshrrev_b64
-;GCN: s_endpgm
define amdgpu_kernel void @test_urem3264(i64 addrspace(1)* %out, i64 %x, i64 %y) {
%1 = lshr i64 %x, 33
%2 = lshr i64 %y, 33
@@ -131,17 +100,12 @@ define amdgpu_kernel void @test_urem3264(i64 addrspace(1)* %out, i64 %x, i64 %y)
ret void
}
-;FUNC-LABEL: {{^}}test_udiv2364:
+;EG-LABEL: {{^}}test_udiv2364:
;EG: UINT_TO_FLT
;EG: UINT_TO_FLT
;EG: FLT_TO_UINT
;EG-NOT: RECIP_UINT
;EG-NOT: BFE_UINT
-
-;SI-NOT: v_lshr_b64
-;VI-NOT: v_lshrrev_b64
-;GCN: v_mad_f32
-;GCN: s_endpgm
define amdgpu_kernel void @test_udiv2364(i64 addrspace(1)* %out, i64 %x, i64 %y) {
%1 = lshr i64 %x, 41
%2 = lshr i64 %y, 41
@@ -150,17 +114,12 @@ define amdgpu_kernel void @test_udiv2364(i64 addrspace(1)* %out, i64 %x, i64 %y)
ret void
}
-;FUNC-LABEL: {{^}}test_urem2364:
+;EG-LABEL: {{^}}test_urem2364:
;EG: UINT_TO_FLT
;EG: UINT_TO_FLT
;EG: FLT_TO_UINT
;EG-NOT: RECIP_UINT
;EG-NOT: BFE_UINT
-
-;SI-NOT: v_lshr_b64
-;VI-NOT: v_lshrrev_b64
-;GCN: v_mad_f32
-;GCN: s_endpgm
define amdgpu_kernel void @test_urem2364(i64 addrspace(1)* %out, i64 %x, i64 %y) {
%1 = lshr i64 %x, 41
%2 = lshr i64 %y, 41
@@ -169,14 +128,7 @@ define amdgpu_kernel void @test_urem2364(i64 addrspace(1)* %out, i64 %x, i64 %y)
ret void
}
-;FUNC-LABEL: {{^}}test_udiv_k:
-;GCN: v_mul{{.+}} v{{[0-9]+}}, v{{[0-9]+}}, 24
-;GCN: v_mul{{.+}} v{{[0-9]+}}, v{{[0-9]+}}, 24
-;GCN: v_mul{{.+}} v{{[0-9]+}}, v{{[0-9]+}}, 24
-;GCN: v_add
-;GCN: v_addc
-;GCN: v_addc
-;GCN: s_endpgm
+;EG-LABEL: {{^}}test_udiv_k:
define amdgpu_kernel void @test_udiv_k(i64 addrspace(1)* %out, i64 %x) {
%result = udiv i64 24, %x
store i64 %result, i64 addrspace(1)* %out
diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll
new file mode 100644
index 000000000000..220f6ad57dde
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/urem64.ll
@@ -0,0 +1,978 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_urem_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s4, s8
+; GCN-NEXT: s_mov_b32 s5, s9
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3
+; GCN-NEXT: s_sub_u32 s8, 0, s2
+; GCN-NEXT: v_mov_b32_e32 v4, s3
+; GCN-NEXT: v_mov_b32_e32 v5, s11
+; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; GCN-NEXT: s_subb_u32 s9, 0, s3
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
+; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_lo_u32 v6, s8, v3
+; GCN-NEXT: v_mul_lo_u32 v7, s9, v2
+; GCN-NEXT: v_mul_hi_u32 v8, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v9, s8, v2
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT: v_mul_hi_u32 v8, v2, v9
+; GCN-NEXT: v_mul_hi_u32 v10, v3, v9
+; GCN-NEXT: v_mul_lo_u32 v9, v3, v9
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GCN-NEXT: v_mul_hi_u32 v7, v2, v6
+; GCN-NEXT: v_mul_lo_u32 v11, v2, v6
+; GCN-NEXT: v_mul_hi_u32 v12, v3, v6
+; GCN-NEXT: v_mul_lo_u32 v6, v3, v6
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v10, vcc
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc
+; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v6
+; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v8, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v9, s9, v2
+; GCN-NEXT: v_mul_lo_u32 v10, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v11, s8, v6
+; GCN-NEXT: v_mul_hi_u32 v12, v6, v10
+; GCN-NEXT: v_mul_lo_u32 v13, v6, v10
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v10
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_mul_hi_u32 v9, v6, v8
+; GCN-NEXT: v_mul_hi_u32 v11, v2, v8
+; GCN-NEXT: v_mul_lo_u32 v14, v2, v8
+; GCN-NEXT: v_mul_lo_u32 v6, v6, v8
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v14
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v1, v11, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v13, v8
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v12, vcc
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v9, vcc
+; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v7, s[0:1]
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, s10, v2
+; GCN-NEXT: v_mul_hi_u32 v7, s11, v2
+; GCN-NEXT: v_mul_lo_u32 v2, s11, v2
+; GCN-NEXT: v_mul_hi_u32 v8, s10, v3
+; GCN-NEXT: v_mul_lo_u32 v9, s10, v3
+; GCN-NEXT: v_mul_hi_u32 v10, s11, v3
+; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v9
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, v8, v7, vcc
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v10, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc
+; GCN-NEXT: v_mul_hi_u32 v1, s2, v2
+; GCN-NEXT: v_mul_lo_u32 v3, s3, v2
+; GCN-NEXT: v_mul_lo_u32 v2, s2, v2
+; GCN-NEXT: v_mul_lo_u32 v0, s2, v0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s11, v0
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, s10, v2
+; GCN-NEXT: v_subb_u32_e64 v1, s[0:1], v1, v4, vcc
+; GCN-NEXT: v_subb_u32_e32 v0, vcc, v5, v0, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
+; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s2, v2
+; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v1, v4, vcc
+; GCN-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v5
+; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v7, vcc, s2, v5
+; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v0
+; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
+; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1]
+; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v0
+; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
+; GCN-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3
+; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %result = urem i64 %x, %y
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define i64 @v_test_urem_i64(i64 %x, i64 %y) {
+; GCN-LABEL: v_test_urem_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2
+; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
+; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc
+; GCN-NEXT: v_mov_b32_e32 v8, 0
+; GCN-NEXT: v_mov_b32_e32 v9, 0
+; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
+; GCN-NEXT: v_rcp_f32_e32 v4, v4
+; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
+; GCN-NEXT: v_trunc_f32_e32 v5, v5
+; GCN-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GCN-NEXT: v_mul_lo_u32 v10, v6, v5
+; GCN-NEXT: v_mul_lo_u32 v11, v7, v4
+; GCN-NEXT: v_mul_hi_u32 v12, v6, v4
+; GCN-NEXT: v_mul_lo_u32 v13, v6, v4
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v12, v10
+; GCN-NEXT: v_mul_hi_u32 v12, v4, v13
+; GCN-NEXT: v_mul_hi_u32 v14, v5, v13
+; GCN-NEXT: v_mul_lo_u32 v13, v5, v13
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v11
+; GCN-NEXT: v_mul_hi_u32 v11, v4, v10
+; GCN-NEXT: v_mul_lo_u32 v15, v4, v10
+; GCN-NEXT: v_mul_hi_u32 v16, v5, v10
+; GCN-NEXT: v_mul_lo_u32 v10, v5, v10
+; GCN-NEXT: v_add_i32_e32 v12, vcc, v12, v15
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v9, v11, vcc
+; GCN-NEXT: v_add_i32_e32 v12, vcc, v13, v12
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v11, v14, vcc
+; GCN-NEXT: v_addc_u32_e32 v12, vcc, v16, v8, vcc
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GCN-NEXT: v_addc_u32_e32 v11, vcc, v9, v12, vcc
+; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v10
+; GCN-NEXT: v_addc_u32_e64 v10, vcc, v5, v11, s[4:5]
+; GCN-NEXT: v_mul_hi_u32 v12, v6, v4
+; GCN-NEXT: v_mul_lo_u32 v7, v7, v4
+; GCN-NEXT: v_mul_lo_u32 v13, v6, v4
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v11
+; GCN-NEXT: v_mul_lo_u32 v6, v6, v10
+; GCN-NEXT: v_mul_hi_u32 v11, v10, v13
+; GCN-NEXT: v_mul_lo_u32 v14, v10, v13
+; GCN-NEXT: v_mul_hi_u32 v13, v4, v13
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v12, v6
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GCN-NEXT: v_mul_hi_u32 v7, v10, v6
+; GCN-NEXT: v_mul_hi_u32 v12, v4, v6
+; GCN-NEXT: v_mul_lo_u32 v15, v4, v6
+; GCN-NEXT: v_mul_lo_u32 v6, v10, v6
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v13, v15
+; GCN-NEXT: v_addc_u32_e32 v12, vcc, v9, v12, vcc
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v14, v10
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v12, v11, vcc
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc
+; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, v0, v4
+; GCN-NEXT: v_mul_hi_u32 v7, v1, v4
+; GCN-NEXT: v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT: v_mul_hi_u32 v10, v0, v5
+; GCN-NEXT: v_mul_lo_u32 v11, v0, v5
+; GCN-NEXT: v_mul_hi_u32 v12, v1, v5
+; GCN-NEXT: v_mul_lo_u32 v5, v1, v5
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v11
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v9, v10, vcc
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
+; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v7, vcc
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v12, v8, vcc
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
+; GCN-NEXT: v_mul_lo_u32 v7, v3, v4
+; GCN-NEXT: v_mul_lo_u32 v4, v2, v4
+; GCN-NEXT: v_mul_lo_u32 v5, v2, v5
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, v1, v5
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
+; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v6, v3, vcc
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
+; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, v0, v2
+; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v4, v3, vcc
+; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v2
+; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, v6, v2
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3
+; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v3
+; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v3
+; GCN-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[4:5]
+; GCN-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v10, v8, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5]
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = urem i64 %x, %y
+ ret i64 %result
+}
+
+define amdgpu_kernel void @s_test_urem31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_urem31_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s2, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s11, 0xf000
+; GCN-NEXT: s_mov_b32 s10, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s8, s4
+; GCN-NEXT: s_mov_b32 s9, s5
+; GCN-NEXT: s_lshr_b32 s3, s7, 1
+; GCN-NEXT: s_lshr_b32 s4, s2, 1
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s4
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s4
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s3
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s4
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s3, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, s4, v1
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s3, v0
+; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s4, v1
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s4, v1
+; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GCN-NEXT: s_endpgm
+ %1 = lshr i64 %x, 33
+ %2 = lshr i64 %y, 33
+ %result = urem i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_urem31_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
+; GCN-LABEL: s_test_urem31_v2i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
+; GCN-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0xd
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11
+; GCN-NEXT: s_mov_b32 s11, 0xf000
+; GCN-NEXT: s_mov_b32 s10, -1
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_lshr_b32 s4, s13, 1
+; GCN-NEXT: s_lshr_b32 s6, s15, 1
+; GCN-NEXT: s_lshr_b32 s12, s5, 1
+; GCN-NEXT: s_lshr_b32 s5, s7, 1
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s12
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_hi_u32 v3, v0, s5
+; GCN-NEXT: v_mul_lo_u32 v4, v0, s5
+; GCN-NEXT: v_mul_hi_u32 v5, v2, s12
+; GCN-NEXT: v_mul_lo_u32 v6, v2, s12
+; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v4
+; GCN-NEXT: v_sub_i32_e32 v8, vcc, 0, v6
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3
+; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v7, s[0:1]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v5
+; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v8, s[2:3]
+; GCN-NEXT: v_mul_hi_u32 v3, v3, v0
+; GCN-NEXT: v_mul_hi_u32 v4, v4, v2
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v3, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v3, v0
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v2
+; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v4, v2
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[2:3]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s6
+; GCN-NEXT: v_mul_hi_u32 v2, v2, s4
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s5
+; GCN-NEXT: v_mul_lo_u32 v2, v2, s12
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, s6, v0
+; GCN-NEXT: v_sub_i32_e32 v4, vcc, s4, v2
+; GCN-NEXT: v_add_i32_e32 v5, vcc, s5, v3
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s6, v0
+; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s5, v3
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s5, v3
+; GCN-NEXT: v_add_i32_e32 v6, vcc, s12, v4
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], s4, v2
+; GCN-NEXT: v_cmp_le_u32_e64 s[6:7], s12, v4
+; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s12, v4
+; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GCN-NEXT: s_and_b64 vcc, s[6:7], s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v0, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v0, v6, v3, s[4:5]
+; GCN-NEXT: v_mov_b32_e32 v3, v1
+; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GCN-NEXT: s_endpgm
+ %1 = lshr <2 x i64> %x, <i64 33, i64 33>
+ %2 = lshr <2 x i64> %y, <i64 33, i64 33>
+ %result = urem <2 x i64> %1, %2
+ store <2 x i64> %result, <2 x i64> addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_urem24_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+; GCN-LABEL: s_test_urem24_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_load_dword s2, s[0:1], 0xe
+; GCN-NEXT: s_mov_b32 s11, 0xf000
+; GCN-NEXT: s_mov_b32 s10, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s8, s4
+; GCN-NEXT: s_mov_b32 s9, s5
+; GCN-NEXT: s_lshr_b32 s3, s7, 8
+; GCN-NEXT: s_lshr_b32 s4, s2, 8
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s4
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s4
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s3
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s4
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s3, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, s4, v1
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s3, v0
+; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s4, v1
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s4, v1
+; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GCN-NEXT: s_endpgm
+ %1 = lshr i64 %x, 40
+ %2 = lshr i64 %y, 40
+ %result = urem i64 %1, %2
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_urem23_64_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
+; GCN-LABEL: s_test_urem23_64_v2i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
+; GCN-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x11
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_lshr_b32 s2, s11, 9
+; GCN-NEXT: s_lshr_b32 s3, s9, 1
+; GCN-NEXT: s_lshr_b32 s8, s15, 9
+; GCN-NEXT: s_lshr_b32 s9, s13, 1
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, s8
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v3
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_mul_f32_e32 v4, v2, v4
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_trunc_f32_e32 v4, v4
+; GCN-NEXT: v_mul_hi_u32 v5, v0, s9
+; GCN-NEXT: v_mul_lo_u32 v6, v0, s9
+; GCN-NEXT: v_mad_f32 v2, -v4, v3, v2
+; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v6
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v3|
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v5
+; GCN-NEXT: v_cndmask_b32_e64 v3, v6, v7, s[0:1]
+; GCN-NEXT: v_mul_lo_u32 v2, v2, s8
+; GCN-NEXT: v_mul_hi_u32 v3, v3, v0
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v3, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v3, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s3
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s9
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, s3, v0
+; GCN-NEXT: v_add_i32_e32 v4, vcc, s9, v3
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s3, v0
+; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s9, v3
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s9, v3
+; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[0:1]
+; GCN-NEXT: v_and_b32_e32 v2, 0x7fffff, v2
+; GCN-NEXT: v_mov_b32_e32 v3, v1
+; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %1 = lshr <2 x i64> %x, <i64 33, i64 41>
+ %2 = lshr <2 x i64> %y, <i64 33, i64 41>
+ %result = urem <2 x i64> %1, %2
+ store <2 x i64> %result, <2 x i64> addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_urem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
+; GCN-LABEL: s_test_urem_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3
+; GCN-NEXT: s_sub_u32 s8, 0, s2
+; GCN-NEXT: v_mov_b32_e32 v4, s3
+; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; GCN-NEXT: s_subb_u32 s9, 0, s3
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
+; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_lo_u32 v5, s8, v3
+; GCN-NEXT: v_mul_lo_u32 v6, s9, v2
+; GCN-NEXT: v_mul_hi_u32 v7, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v8, s8, v2
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GCN-NEXT: v_mul_hi_u32 v7, v2, v8
+; GCN-NEXT: v_mul_hi_u32 v9, v3, v8
+; GCN-NEXT: v_mul_lo_u32 v8, v3, v8
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
+; GCN-NEXT: v_mul_hi_u32 v6, v2, v5
+; GCN-NEXT: v_mul_lo_u32 v10, v2, v5
+; GCN-NEXT: v_mul_hi_u32 v11, v3, v5
+; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v6, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v9, vcc
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v7, vcc
+; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v5
+; GCN-NEXT: v_addc_u32_e64 v5, vcc, v3, v6, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v7, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v8, s9, v2
+; GCN-NEXT: v_mul_lo_u32 v9, s8, v2
+; GCN-NEXT: v_mul_lo_u32 v10, s8, v5
+; GCN-NEXT: v_mul_hi_u32 v11, v5, v9
+; GCN-NEXT: v_mul_lo_u32 v12, v5, v9
+; GCN-NEXT: v_mul_hi_u32 v9, v2, v9
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT: v_mul_hi_u32 v8, v5, v7
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v7
+; GCN-NEXT: v_mul_lo_u32 v13, v2, v7
+; GCN-NEXT: v_mul_lo_u32 v5, v5, v7
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v13
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v1, v10, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v12, v7
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v11, vcc
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v0, vcc
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v8, vcc
+; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v2, v2, 24
+; GCN-NEXT: v_mul_hi_u32 v5, v3, 24
+; GCN-NEXT: v_mul_lo_u32 v3, v3, 24
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
+; GCN-NEXT: v_mul_hi_u32 v2, s2, v1
+; GCN-NEXT: v_mul_lo_u32 v3, s3, v1
+; GCN-NEXT: v_mul_lo_u32 v1, s2, v1
+; GCN-NEXT: v_mul_lo_u32 v0, s2, v0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0, v0
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 24, v1
+; GCN-NEXT: v_subb_u32_e64 v1, s[0:1], v2, v4, vcc
+; GCN-NEXT: v_subb_u32_e32 v0, vcc, 0, v0, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
+; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s2, v3
+; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v1, v4, vcc
+; GCN-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v5
+; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v7, vcc, s2, v5
+; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v0
+; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
+; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1]
+; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v0
+; GCN-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
+; GCN-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
+; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1]
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %result = urem i64 24, %x
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
+; GCN-LABEL: s_test_urem_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000
+; GCN-NEXT: s_movk_i32 s8, 0xffe8
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: v_mov_b32_e32 v2, 0
+; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000
+; GCN-NEXT: v_rcp_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
+; GCN-NEXT: v_mov_b32_e32 v4, s3
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_lo_u32 v5, v3, s8
+; GCN-NEXT: v_mul_hi_u32 v6, v0, s8
+; GCN-NEXT: v_mul_lo_u32 v7, v0, s8
+; GCN-NEXT: v_subrev_i32_e32 v6, vcc, v0, v6
+; GCN-NEXT: v_mul_hi_u32 v8, v0, v7
+; GCN-NEXT: v_mul_hi_u32 v9, v3, v7
+; GCN-NEXT: v_mul_lo_u32 v7, v3, v7
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
+; GCN-NEXT: v_mul_hi_u32 v6, v0, v5
+; GCN-NEXT: v_mul_lo_u32 v10, v0, v5
+; GCN-NEXT: v_mul_hi_u32 v11, v3, v5
+; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v9, vcc
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v1, vcc
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v7, vcc
+; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v5
+; GCN-NEXT: v_addc_u32_e64 v5, vcc, v3, v6, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v7, v0, s8
+; GCN-NEXT: v_mul_lo_u32 v8, v0, s8
+; GCN-NEXT: v_mul_lo_u32 v9, v5, s8
+; GCN-NEXT: v_subrev_i32_e32 v7, vcc, v0, v7
+; GCN-NEXT: v_mul_hi_u32 v10, v0, v8
+; GCN-NEXT: v_mul_hi_u32 v11, v5, v8
+; GCN-NEXT: v_mul_lo_u32 v8, v5, v8
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT: v_mul_hi_u32 v9, v0, v7
+; GCN-NEXT: v_mul_lo_u32 v12, v0, v7
+; GCN-NEXT: v_mul_hi_u32 v13, v5, v7
+; GCN-NEXT: v_mul_lo_u32 v5, v5, v7
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v12
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v9, vcc
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v11, vcc
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v1, vcc
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v8, vcc
+; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v5
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v5, s2, v0
+; GCN-NEXT: v_mul_hi_u32 v6, s3, v0
+; GCN-NEXT: v_mul_lo_u32 v0, s3, v0
+; GCN-NEXT: v_mul_hi_u32 v7, s2, v3
+; GCN-NEXT: v_mul_lo_u32 v8, s2, v3
+; GCN-NEXT: v_mul_hi_u32 v9, s3, v3
+; GCN-NEXT: v_mul_lo_u32 v3, s3, v3
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v7, vcc
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v5
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, v7, v6, vcc
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v9, v1, vcc
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; GCN-NEXT: v_mul_hi_u32 v2, v0, 24
+; GCN-NEXT: v_mul_lo_u32 v0, v0, 24
+; GCN-NEXT: v_mul_lo_u32 v1, v1, 24
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
+; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v0
+; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[0:1]
+; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v5, vcc, 24, v2
+; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v2
+; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v3, -1, v3, s[0:1]
+; GCN-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v4, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GCN-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3
+; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %result = urem i64 %x, 24
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+; FIXME: Constant bus violation
+; define i64 @v_test_urem_k_num_i64(i64 %x) {
+; %result = urem i64 24, %x
+; ret i64 %result
+; }
+
+define i64 @v_test_urem_pow2_k_num_i64(i64 %x) {
+; GCN-LABEL: v_test_urem_pow2_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1
+; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v0
+; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc
+; GCN-NEXT: v_mov_b32_e32 v6, 0
+; GCN-NEXT: v_mov_b32_e32 v7, 0
+; GCN-NEXT: s_mov_b32 s6, 0x8000
+; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
+; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_lo_u32 v8, v4, v3
+; GCN-NEXT: v_mul_lo_u32 v9, v5, v2
+; GCN-NEXT: v_mul_hi_u32 v10, v4, v2
+; GCN-NEXT: v_mul_lo_u32 v11, v4, v2
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v11
+; GCN-NEXT: v_mul_hi_u32 v12, v3, v11
+; GCN-NEXT: v_mul_lo_u32 v11, v3, v11
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9
+; GCN-NEXT: v_mul_hi_u32 v9, v2, v8
+; GCN-NEXT: v_mul_lo_u32 v13, v2, v8
+; GCN-NEXT: v_mul_hi_u32 v14, v3, v8
+; GCN-NEXT: v_mul_lo_u32 v8, v3, v8
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v13
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v9, vcc
+; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v12, vcc
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v6, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc
+; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v8
+; GCN-NEXT: v_addc_u32_e64 v8, vcc, v3, v9, s[4:5]
+; GCN-NEXT: v_mul_hi_u32 v10, v4, v2
+; GCN-NEXT: v_mul_lo_u32 v5, v5, v2
+; GCN-NEXT: v_mul_lo_u32 v11, v4, v2
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v9
+; GCN-NEXT: v_mul_lo_u32 v4, v4, v8
+; GCN-NEXT: v_mul_hi_u32 v9, v8, v11
+; GCN-NEXT: v_mul_lo_u32 v12, v8, v11
+; GCN-NEXT: v_mul_hi_u32 v11, v2, v11
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v10, v4
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
+; GCN-NEXT: v_mul_hi_u32 v5, v8, v4
+; GCN-NEXT: v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT: v_mul_lo_u32 v13, v2, v4
+; GCN-NEXT: v_mul_lo_u32 v4, v8, v4
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v11, v13
+; GCN-NEXT: v_addc_u32_e32 v10, vcc, v7, v10, vcc
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v12, v8
+; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v9, vcc
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc
+; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc
+; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2
+; GCN-NEXT: v_mul_lo_u32 v3, v1, v2
+; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
+; GCN-NEXT: v_mul_lo_u32 v2, v0, v2
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
+; GCN-NEXT: v_sub_i32_e64 v4, s[4:5], 0, v3
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v0
+; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
+; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
+; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, v2, v0
+; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v4, v1, vcc
+; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0
+; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v6, v0
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v1
+; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v1
+; GCN-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[4:5]
+; GCN-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v4, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v10, v8, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5]
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = urem i64 32768, %x
+ ret i64 %result
+}
+
+define i64 @v_test_urem_pow2_k_den_i64(i64 %x) {
+; GCN-LABEL: v_test_urem_pow2_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %result = urem i64 %x, 32768
+ ret i64 %result
+}
+
+define amdgpu_kernel void @s_test_urem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
+; GCN-LABEL: s_test_urem24_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: s_lshr_b32 s8, s3, 8
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s8
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s8
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, 24
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s8
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, 24, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, s8, v1
+; GCN-NEXT: v_cmp_gt_u32_e64 s[0:1], 25, v0
+; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s8, v1
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s8, v1
+; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %x.shr = lshr i64 %x, 40
+ %result = urem i64 24, %x.shr
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
+; GCN-LABEL: s_test_urem24_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_movk_i32 s2, 0x5b7f
+; GCN-NEXT: s_movk_i32 s8, 0x5b7e
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: s_lshr_b32 s3, s3, 8
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, s2
+; GCN-NEXT: v_mul_lo_u32 v2, v0, s2
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s3
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s2
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s3, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, s2, v1
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s3, v0
+; GCN-NEXT: v_cmp_lt_u32_e64 s[2:3], s8, v1
+; GCN-NEXT: v_add_i32_e32 v0, vcc, 0xffffa481, v1
+; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %x.shr = lshr i64 %x, 40
+ %result = urem i64 %x.shr, 23423
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
+
+define i64 @v_test_urem24_k_num_i64(i64 %x) {
+; GCN-LABEL: v_test_urem24_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
+; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
+; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GCN-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GCN-NEXT: v_mul_hi_u32 v2, v1, v0
+; GCN-NEXT: v_mul_lo_u32 v3, v1, v0
+; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GCN-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; GCN-NEXT: v_mul_hi_u32 v2, v2, v1
+; GCN-NEXT: v_add_i32_e64 v3, s[4:5], v1, v2
+; GCN-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v1, v1, 24
+; GCN-NEXT: v_mul_lo_u32 v1, v1, v0
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, 24, v1
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v2, v0
+; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 25, v1
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v0
+; GCN-NEXT: v_sub_i32_e64 v0, s[6:7], v2, v0
+; GCN-NEXT: s_and_b64 s[4:5], s[4:5], vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %x.shr = lshr i64 %x, 40
+ %result = urem i64 24, %x.shr
+ ret i64 %result
+}
+
+define i64 @v_test_urem24_pow2_k_num_i64(i64 %x) {
+; GCN-LABEL: v_test_urem24_pow2_k_num_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
+; GCN-NEXT: s_mov_b32 s6, 0x8001
+; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
+; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GCN-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GCN-NEXT: v_mul_hi_u32 v2, v1, v0
+; GCN-NEXT: v_mul_lo_u32 v3, v1, v0
+; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GCN-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; GCN-NEXT: v_mul_hi_u32 v2, v2, v1
+; GCN-NEXT: v_add_i32_e64 v3, s[4:5], v1, v2
+; GCN-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v1, 17, v1
+; GCN-NEXT: v_mul_u32_u24_e32 v1, v1, v0
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0x8000, v1
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v2, v0
+; GCN-NEXT: v_cmp_gt_u32_e32 vcc, s6, v1
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v0
+; GCN-NEXT: v_sub_i32_e64 v0, s[6:7], v2, v0
+; GCN-NEXT: s_and_b64 s[4:5], s[4:5], vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %x.shr = lshr i64 %x, 40
+ %result = urem i64 32768, %x.shr
+ ret i64 %result
+}
+
+define i64 @v_test_urem24_pow2_k_den_i64(i64 %x) {
+; GCN-LABEL: v_test_urem24_pow2_k_den_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_bfe_u32 v0, v1, 8, 15
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %x.shr = lshr i64 %x, 40
+ %result = urem i64 %x.shr, 32768
+ ret i64 %result
+}
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